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| author | azidar | 2015-04-29 11:42:37 -0700 |
|---|---|---|
| committer | azidar | 2015-04-29 11:42:37 -0700 |
| commit | ddc0dfe7a5f942ad1066b86b4f3ba9494493c6ed (patch) | |
| tree | c440e3569707a0451da1330a2fd036718c36a9d7 /test/passes/infer-widths/dsh.fir | |
| parent | c46608d92bd493fa33c3c5122341c716ca75ecb0 (diff) | |
Added dshl and dshr
Diffstat (limited to 'test/passes/infer-widths/dsh.fir')
| -rw-r--r-- | test/passes/infer-widths/dsh.fir | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/test/passes/infer-widths/dsh.fir b/test/passes/infer-widths/dsh.fir new file mode 100644 index 00000000..1eb23115 --- /dev/null +++ b/test/passes/infer-widths/dsh.fir @@ -0,0 +1,25 @@ +; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p ctd | tee %s.out | FileCheck %s + +;CHECK: Infer Widths + +circuit top : + module M : + wire x : UInt<16> + wire z : SInt<16> + wire y : UInt<3> + wire a : UInt + wire b : SInt + wire c : UInt + wire d : SInt + + a := dshl-u(x,y) + b := dshl-s(z,y) + c := dshr-u(x,y) + d := dshr-s(z,y) + + +; CHECK: wire a : UInt<23> +; CHECK: wire b : SInt<23> +; CHECK: wire c : UInt<16> +; CHECK: wire d : SInt<16> +; CHECK: Finished Infer Widths |