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authorazidar2015-08-17 13:35:24 -0700
committerazidar2015-08-17 13:35:24 -0700
commitc7e4b472787cb9702dd4fbec53eb231bdf81b4d1 (patch)
tree9c0e400d8f35f35c21e56440d5b36db849577aea /test/passes/expand-whens
parent3cbffd9006e156ac2f7cd61702ce7f99360fcbd0 (diff)
Added tests for shl and mem. Fixed bug in verilog output of mem size.
Diffstat (limited to 'test/passes/expand-whens')
-rw-r--r--test/passes/expand-whens/wacc-wdc.fir1
1 files changed, 0 insertions, 1 deletions
diff --git a/test/passes/expand-whens/wacc-wdc.fir b/test/passes/expand-whens/wacc-wdc.fir
index b7b6e9fa..127e10ed 100644
--- a/test/passes/expand-whens/wacc-wdc.fir
+++ b/test/passes/expand-whens/wacc-wdc.fir
@@ -1,5 +1,4 @@
; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
-; XFAIL: *
circuit top :
module top :
input clk : Clock