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authorjackbackrack2015-06-02 08:47:40 -0700
committerjackbackrack2015-06-02 08:47:40 -0700
commitb178ca42fd9d4f7b94d80c01cd810bf18da9ebc8 (patch)
tree033e197aa2e297187e21712faf1957eb405b435b /test/passes/expand-whens
parente668a13b285c87678a708a8af5bee2cfa0f7645b (diff)
parent8fc826a2770f46d63d8d7b1bccf14d2bf6e6b7cd (diff)
merge + fix trim to use correct bits operands
Diffstat (limited to 'test/passes/expand-whens')
-rw-r--r--test/passes/expand-whens/bundle-init.fir8
-rw-r--r--test/passes/expand-whens/nested-whens.fir2
-rw-r--r--test/passes/expand-whens/one-when.fir2
-rw-r--r--test/passes/expand-whens/two-when.fir2
4 files changed, 7 insertions, 7 deletions
diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir
index c51604eb..4f8c31e2 100644
--- a/test/passes/expand-whens/bundle-init.fir
+++ b/test/passes/expand-whens/bundle-init.fir
@@ -15,11 +15,11 @@ circuit top :
r.y := b
on-reset r := w
-; CHECK: node r_x = Register(mux(reset, w_x, a), UInt(1))
-; CHECK: node r_y = Register(b, UInt(1))
+; CHECK: r$x := Register(mux(reset, w$x, a), UInt(1))
+; CHECK: r$y := Register(b, UInt(1))
; CHECK: a := UInt(1)
; CHECK: b := UInt(2)
-; CHECK: w_x := b
-; CHECK: w_y := mux(reset, r_y, a)
+; CHECK: w$x := b
+; CHECK: w$y := mux(reset, r$y, a)
; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir
index 21a6f24b..f7ac8337 100644
--- a/test/passes/expand-whens/nested-whens.fir
+++ b/test/passes/expand-whens/nested-whens.fir
@@ -20,5 +20,5 @@ circuit top :
on-reset r := y
r := b
r := z
-; CHECK: node r = Register(mux(reset, mux(q, y, mux(p, x, w)), z), UInt(1))
+; CHECK: r := Register(mux(reset, mux(q, y, mux(p, x, w)), z), UInt(1))
; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir
index 718f1d4b..114e5b5b 100644
--- a/test/passes/expand-whens/one-when.fir
+++ b/test/passes/expand-whens/one-when.fir
@@ -3,7 +3,7 @@
; CHECK: Expand Whens
circuit top :
module top :
- mem m : UInt<1>[2]
+ cmem m : UInt<1>[2]
wire i : UInt<1>
wire p : UInt<1>
wire j : UInt<1>
diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir
index 7bee8444..fb537303 100644
--- a/test/passes/expand-whens/two-when.fir
+++ b/test/passes/expand-whens/two-when.fir
@@ -3,7 +3,7 @@
; CHECK: Expand Whens
circuit top :
module top :
- mem m :{ x : UInt<1>, y : UInt<1> }[2]
+ cmem m :{ x : UInt<1>, y : UInt<1> }[2]
wire i : UInt<1>
wire p : UInt<1>
wire q : { x : UInt<1>, y : UInt<1> }