diff options
| author | azidar | 2015-08-18 15:37:30 -0700 |
|---|---|---|
| committer | azidar | 2015-08-18 15:37:30 -0700 |
| commit | 6253cb0880a39a046417490ae42da3789a2b5a27 (patch) | |
| tree | 65cf5971f767307e29dfc23765fb6e2b49a3b066 /test/passes/expand-whens | |
| parent | dc80d4f52a76aab8fcf0053b988658dd3857270c (diff) | |
Fixed so its length is greater than what it connects to. Changed shr to be extract, not >>
Diffstat (limited to 'test/passes/expand-whens')
| -rw-r--r-- | test/passes/expand-whens/bundle-init.fir | 4 | ||||
| -rw-r--r-- | test/passes/expand-whens/reg-dwc.fir | 4 | ||||
| -rw-r--r-- | test/passes/expand-whens/reg-dwoc.fir | 4 | ||||
| -rw-r--r-- | test/passes/expand-whens/wacc-wdc.fir | 6 |
4 files changed, 9 insertions, 9 deletions
diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir index f7b14c0f..21bbbc52 100644 --- a/test/passes/expand-whens/bundle-init.fir +++ b/test/passes/expand-whens/bundle-init.fir @@ -19,8 +19,8 @@ circuit top : ; CHECK: r$x := mux(reset, w$x, a) ; CHECK: r$y := mux(reset, w$y, b) -; CHECK: a := UInt("h00000001") -; CHECK: b := UInt("h00000002") +; CHECK: a := UInt("h1") +; CHECK: b := UInt("h2") ; CHECK: w$x := b ; CHECK: w$y := a diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir index f8076a3e..2403816a 100644 --- a/test/passes/expand-whens/reg-dwc.fir +++ b/test/passes/expand-whens/reg-dwc.fir @@ -15,8 +15,8 @@ circuit top : ; CHECK: module top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt -; CHECK: p := UInt("h00000001") -; CHECK: when p : r := UInt("h00000002") +; CHECK: p := UInt("h1") +; CHECK: when p : r := UInt("h2") ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/reg-dwoc.fir b/test/passes/expand-whens/reg-dwoc.fir index 0defc432..a32985b6 100644 --- a/test/passes/expand-whens/reg-dwoc.fir +++ b/test/passes/expand-whens/reg-dwoc.fir @@ -16,8 +16,8 @@ circuit top : ; CHECK: module top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt, clk, reset -; CHECK: p := UInt("h00000001") -; CHECK: when p : r := mux(reset, UInt("h00000001"), UInt("h00000002")) +; CHECK: p := UInt("h1") +; CHECK: when p : r := mux(reset, UInt("h1"), UInt("h2")) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/wacc-wdc.fir b/test/passes/expand-whens/wacc-wdc.fir index 127e10ed..001f2f25 100644 --- a/test/passes/expand-whens/wacc-wdc.fir +++ b/test/passes/expand-whens/wacc-wdc.fir @@ -15,9 +15,9 @@ circuit top : ; CHECK: module top : ; CHECK: wire p : UInt ; CHECK: cmem m : UInt<4>[10], clk -; CHECK: write accessor a = m[UInt("h00000003")] -; CHECK: p := UInt("h00000001") -; CHECK: when p : a := UInt("h00000002") +; CHECK: write accessor a = m[UInt("h3")] +; CHECK: p := UInt("h1") +; CHECK: when p : a := UInt("h2") ; CHECK: Finished Expand Whens |