Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass

11 files changed, 42 insertions, 22 deletions

diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir
index 261ebf02..10da47cf 100644
--- a/test/passes/expand-whens/bundle-init.fir
+++ b/test/passes/expand-whens/bundle-init.fir
@@ -2,7 +2,9 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      reg r : { x : UInt, flip y : UInt}
+      input clk : Clock
+      input reset : UInt<1>
+      reg r : { x : UInt, flip y : UInt},clk,reset
       wire a : UInt
       wire b : UInt
       wire w : { x : UInt, flip y : UInt}
@@ -13,7 +15,7 @@ circuit top :
       w.y := a
       r.x := a
       r.y := b
-      on-reset r := w
+      onreset r := w
 
 ; CHECK: when UInt(1) : r$x := mux(reset, w$x, a)
 ; CHECK: when UInt(1) : r$y := b
diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir
index 4d23a549..c81ca485 100644
--- a/test/passes/expand-whens/nested-whens.fir
+++ b/test/passes/expand-whens/nested-whens.fir
@@ -2,9 +2,11 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
+      input clk : Clock
+      input reset : UInt<1>
       wire p : UInt
       wire q : UInt
-      reg r : UInt
+      reg r : UInt, clk, reset
       wire a : UInt
       wire b : UInt
       wire x : UInt
@@ -20,12 +22,12 @@ circuit top :
       z := UInt(1)
       w := UInt(1)
 
-      on-reset r := w
+      onreset r := w
       when p :
-        on-reset r := x
+        onreset r := x
         r := a
       when q :
-        on-reset r := y
+        onreset r := y
         r := b
       r := z
 ; CHECK: when UInt(1) : r := mux(reset, mux(q, y, mux(p, x, w)), z)
diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir
index 4e6ea1e5..1332395c 100644
--- a/test/passes/expand-whens/one-when.fir
+++ b/test/passes/expand-whens/one-when.fir
@@ -3,16 +3,18 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      cmem m : UInt<1>[2]
+      input clk : Clock
+      input reset : UInt<1>
+      cmem m : UInt<1>[2], clk
       wire i : UInt<1>
       wire p : UInt<1>
       wire j : UInt<1>
       j := UInt(1)
-      reg r : UInt<1>
+      reg r : UInt<1>, clk, reset
 
       p := j
       when p :
-        on-reset r := i
+        onreset r := i
         infer accessor a = m[i] 
         i := a
         infer accessor b = m[i]
@@ -27,7 +29,7 @@ circuit top :
         p := i
         when e :
            p := p
-           on-reset r := p
+           onreset r := p
            r := p
         
 
diff --git a/test/passes/expand-whens/partial-init.fir b/test/passes/expand-whens/partial-init.fir
index 03b1f965..f752eccd 100644
--- a/test/passes/expand-whens/partial-init.fir
+++ b/test/passes/expand-whens/partial-init.fir
@@ -3,7 +3,9 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      reg r : UInt<1>[10]
+      input clk : Clock
+      input reset : UInt<1>
+      reg r : UInt<1>[10],clk,reset
       r[0] := UInt(1)
       r[1] := UInt(1)
       r[2] := UInt(1)
@@ -14,6 +16,6 @@ circuit top :
       r[7] := UInt(1)
       r[8] := UInt(1)
       r[9] := UInt(1)
-      on-reset r[3] := UInt(0)
+      onreset r[3] := UInt(0)
 
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir
index 01347fdd..ac0f405b 100644
--- a/test/passes/expand-whens/reg-dwc.fir
+++ b/test/passes/expand-whens/reg-dwc.fir
@@ -1,9 +1,11 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
 circuit top :
    module top :
+      input clk : Clock
+      input reset : UInt<1>
       wire p : UInt
       p := UInt(1)
-      reg r : UInt
+      reg r : UInt,clk,reset
       when p :
          r := UInt(20)
 
diff --git a/test/passes/expand-whens/reg-dwoc.fir b/test/passes/expand-whens/reg-dwoc.fir
index 521e1710..ab6f4915 100644
--- a/test/passes/expand-whens/reg-dwoc.fir
+++ b/test/passes/expand-whens/reg-dwoc.fir
@@ -1,9 +1,11 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
 circuit top :
    module top :
+      input clk : Clock
+      input reset : UInt<1>
       wire p : UInt
       p := UInt(1)
-      reg r : UInt
+      reg r : UInt,clk,reset
       when p :
          on-reset r := UInt(10)
          r := UInt(20)
diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir
index df6c7034..03f5ade9 100644
--- a/test/passes/expand-whens/reg-wdc.fir
+++ b/test/passes/expand-whens/reg-wdc.fir
@@ -1,10 +1,12 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
 circuit top :
    module top :
+      input clk : Clock
+      input reset : UInt<1>
       wire p : UInt
       p := UInt(1)
       when p :
-         reg r : UInt
+         reg r : UInt,clk,reset
          r := UInt(20)
 
 ; CHECK: Expand Whens
diff --git a/test/passes/expand-whens/reg-wdoc.fir b/test/passes/expand-whens/reg-wdoc.fir
index ad191a01..1de6d8f4 100644
--- a/test/passes/expand-whens/reg-wdoc.fir
+++ b/test/passes/expand-whens/reg-wdoc.fir
@@ -1,11 +1,13 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
 circuit top :
    module top :
+      input clk : Clock
+      input reset : UInt<1>
       wire p : UInt
       p := UInt(1)
       when p :
-         reg r : UInt
-         on-reset r := UInt(10)
+         reg r : UInt,clk,reset
+         onreset r := UInt(10)
          r := UInt(20)
 
 ; CHECK: Expand Whens
@@ -13,7 +15,7 @@ circuit top :
 ; CHECK: circuit top :
 ; CHECK:   module top :
 ; CHECK:     wire p : UInt
-; CHECK:     reg r : UInt
+; CHECK:     reg r : UInt, clk, reset
 ; CHECK:     p := UInt(1)
 ; CHECK:     r := mux(reset, UInt(10), UInt(20))
 
diff --git a/test/passes/expand-whens/scoped-reg.fir b/test/passes/expand-whens/scoped-reg.fir
index d119932f..aec64871 100644
--- a/test/passes/expand-whens/scoped-reg.fir
+++ b/test/passes/expand-whens/scoped-reg.fir
@@ -1,11 +1,13 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
 circuit top :
    module top :
+      input clk : Clock
+      input reset : UInt<1>
       wire p : UInt
       p := UInt(1)
       when p :
-         reg r : UInt
-         on-reset r := UInt(10)
+         reg r : UInt, clk, reset
+         onreset r := UInt(10)
          r := UInt(20)
 
 ; CHECK: Expand Whens
diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir
index b6c98263..2203f25e 100644
--- a/test/passes/expand-whens/two-when.fir
+++ b/test/passes/expand-whens/two-when.fir
@@ -3,7 +3,8 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      cmem m :{ x : UInt<1>, y : UInt<1> }[2] 
+      input clk : Clock
+      cmem m :{ x : UInt<1>, y : UInt<1> }[2], clk
       wire i : UInt<1>
       i := UInt(1)
       wire p : UInt<1>
diff --git a/test/passes/expand-whens/wacc-wdc.fir b/test/passes/expand-whens/wacc-wdc.fir
index 6e407178..653a3e88 100644
--- a/test/passes/expand-whens/wacc-wdc.fir
+++ b/test/passes/expand-whens/wacc-wdc.fir
@@ -1,8 +1,9 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
 circuit top :
    module top :
+      input clk : Clock
       wire p : UInt
-      cmem m : UInt<4>[10]
+      cmem m : UInt<4>[10], clk
       p := UInt(1)
       when p :
          write accessor a = m[UInt(3)]