New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

12 files changed, 136 insertions, 136 deletions

diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir
index 892b419a..f34dbe1a 100644
--- a/test/passes/expand-whens/bundle-init.fir
+++ b/test/passes/expand-whens/bundle-init.fir
@@ -8,20 +8,20 @@ circuit top :
       wire a : UInt
       wire b : UInt
       wire w : { x : UInt, y : UInt}
-      a := UInt(1)
-      b := UInt(2)
+      a <= UInt(1)
+      b <= UInt(2)
 
-      w.x := b
-      w.y := a
-      r.x := a
-      r.y := b
-      onreset r := w
+      w.x <= b
+      w.y <= a
+      r.x <= a
+      r.y <= b
+      onreset r <= w
 
-; CHECK: r$x := mux(reset, w$x, a)
-; CHECK: r$y := mux(reset, w$y, b)
-; CHECK: a := UInt("h1")
-; CHECK: b := UInt("h2")
-; CHECK: w$x := b
-; CHECK: w$y := a
+; CHECK: r$x <= mux(reset, w$x, a)
+; CHECK: r$y <= mux(reset, w$y, b)
+; CHECK: a <= UInt("h1")
+; CHECK: b <= UInt("h2")
+; CHECK: w$x <= b
+; CHECK: w$y <= a
       
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir
index f5f33af6..0a45dac1 100644
--- a/test/passes/expand-whens/nested-whens.fir
+++ b/test/passes/expand-whens/nested-whens.fir
@@ -13,22 +13,22 @@ circuit top :
       wire y : UInt
       wire z : UInt
       wire w : UInt
-      p := UInt(1)
-      q := UInt(1)
-      a := UInt(1)
-      b := UInt(1)
-      x := UInt(1)
-      y := UInt(1)
-      z := UInt(1)
-      w := UInt(1)
+      p <= UInt(1)
+      q <= UInt(1)
+      a <= UInt(1)
+      b <= UInt(1)
+      x <= UInt(1)
+      y <= UInt(1)
+      z <= UInt(1)
+      w <= UInt(1)
 
-      onreset r := w
+      onreset r <= w
       when p :
-        onreset r := x
-        r := a
+        onreset r <= x
+        r <= a
       when q :
-        onreset r := y
-        r := b
-      r := z
-; CHECK: r := mux(reset, mux(q, y, mux(p, x, w)), z)
+        onreset r <= y
+        r <= b
+      r <= z
+; CHECK: r <= mux(reset, mux(q, y, mux(p, x, w)), z)
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir
index 35fb18be..53616b0e 100644
--- a/test/passes/expand-whens/one-when.fir
+++ b/test/passes/expand-whens/one-when.fir
@@ -9,28 +9,28 @@ circuit top :
       wire i : UInt<1>
       wire p : UInt<1>
       wire j : UInt<1>
-      j := UInt(1)
+      j <= UInt(1)
       reg r : UInt<1>, clk, reset
 
-      p := j
+      p <= j
       when p :
-        onreset r := i
+        onreset r <= i
         infer accessor a = m[i] 
-        i := a
+        i <= a
         infer accessor b = m[i]
-        b := i
+        b <= i
       else :
         infer accessor c = m[i]
-        i := c
+        i <= c
         infer accessor d = m[i] 
-        d := i
+        d <= i
       infer accessor e = m[i]
       when p :
-        p := i
+        p <= i
         when e :
-           p := p
-           onreset r := p
-           r := p
+           p <= p
+           onreset r <= p
+           r <= p
         
 
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/partial-init.fir b/test/passes/expand-whens/partial-init.fir
index 3b5a9f0f..f2b9c2e1 100644
--- a/test/passes/expand-whens/partial-init.fir
+++ b/test/passes/expand-whens/partial-init.fir
@@ -6,16 +6,16 @@ circuit top :
       input clk : Clock
       input reset : UInt<1>
       reg r : UInt<1>[10],clk,reset
-      r[0] := UInt(1)
-      r[1] := UInt(1)
-      r[2] := UInt(1)
-      r[3] := UInt(1)
-      r[4] := UInt(1)
-      r[5] := UInt(1)
-      r[6] := UInt(1)
-      r[7] := UInt(1)
-      r[8] := UInt(1)
-      r[9] := UInt(1)
-      onreset r[3] := UInt(0)
+      r[0] <= UInt(1)
+      r[1] <= UInt(1)
+      r[2] <= UInt(1)
+      r[3] <= UInt(1)
+      r[4] <= UInt(1)
+      r[5] <= UInt(1)
+      r[6] <= UInt(1)
+      r[7] <= UInt(1)
+      r[8] <= UInt(1)
+      r[9] <= UInt(1)
+      onreset r[3] <= UInt(0)
 
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/reg-and-when.fir b/test/passes/expand-whens/reg-and-when.fir
index ac678b6d..97b96735 100644
--- a/test/passes/expand-whens/reg-and-when.fir
+++ b/test/passes/expand-whens/reg-and-when.fir
@@ -12,35 +12,35 @@ circuit Top :
     input set_divisor : {valid : UInt<1>, bits : UInt<32>}
     output divisor : UInt<32>
     
-    out_fast.ready := UInt<1>("h00")
-    out_slow.bits := UInt<1>("h00")
-    out_slow.valid := UInt<1>("h00")
-    in_fast.bits := UInt<1>("h00")
-    in_fast.valid := UInt<1>("h00")
-    in_slow.ready := UInt<1>("h00")
-    clk_slow := UInt<1>("h00")
-    divisor := UInt<1>("h00")
+    out_fast.ready <= UInt<1>("h00")
+    out_slow.bits <= UInt<1>("h00")
+    out_slow.valid <= UInt<1>("h00")
+    in_fast.bits <= UInt<1>("h00")
+    in_fast.valid <= UInt<1>("h00")
+    in_slow.ready <= UInt<1>("h00")
+    clk_slow <= UInt<1>("h00")
+    divisor <= UInt<1>("h00")
     
     inst fromhost_q of Queue_50
-    fromhost_q.reset := UInt<1>("h00")
-    fromhost_q.enq.bits := UInt<1>("h00")
-    fromhost_q.enq.valid := UInt<1>("h00")
-    fromhost_q.deq.ready := UInt<1>("h00")
-    fromhost_q.clock := clock
-    fromhost_q.reset := reset
+    fromhost_q.reset <= UInt<1>("h00")
+    fromhost_q.enq.bits <= UInt<1>("h00")
+    fromhost_q.enq.valid <= UInt<1>("h00")
+    fromhost_q.deq.ready <= UInt<1>("h00")
+    fromhost_q.clock <= clock
+    fromhost_q.reset <= reset
 
     inst tohost_q of Queue_51
-    tohost_q.reset := UInt<1>("h00")
-    tohost_q.enq.bits := UInt<1>("h00")
-    tohost_q.enq.valid := UInt<1>("h00")
-    tohost_q.deq.ready := UInt<1>("h00")
-    tohost_q.clock := clock
-    tohost_q.reset := reset
+    tohost_q.reset <= UInt<1>("h00")
+    tohost_q.enq.bits <= UInt<1>("h00")
+    tohost_q.enq.valid <= UInt<1>("h00")
+    tohost_q.deq.ready <= UInt<1>("h00")
+    tohost_q.clock <= clock
+    tohost_q.reset <= reset
 
     reg out_slow_bits : UInt<17>, clock, reset
-    out_slow_bits := tohost_q.deq.bits
+    out_slow_bits <= tohost_q.deq.bits
     when fromhost_q.deq.valid : 
-      out_slow_bits := fromhost_q.deq.bits
+      out_slow_bits <= fromhost_q.deq.bits
     
   module Queue_50 : 
     input clock : Clock
@@ -49,14 +49,14 @@ circuit Top :
     output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}
     output count : UInt<1>
     
-    enq.ready := UInt<1>("h00")
-    deq.bits := UInt<1>("h00")
-    deq.valid := UInt<1>("h00")
-    count := UInt<1>("h00")
+    enq.ready <= UInt<1>("h00")
+    deq.bits <= UInt<1>("h00")
+    deq.valid <= UInt<1>("h00")
+    count <= UInt<1>("h00")
     
     cmem ram : UInt<17>[1], clock
     reg maybe_full : UInt<1>, clock, reset
-    onreset maybe_full := UInt<1>("h00")
+    onreset maybe_full <= UInt<1>("h00")
     node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00"))
     node T_115167 = eq(maybe_full, UInt<1>("h00"))
     node empty = and(ptr_match, T_115167)
@@ -71,34 +71,34 @@ circuit Top :
     node do_deq = and(T_115177, T_115179)
     when do_enq :
       infer accessor T_115181 = ram[UInt<1>("h00")]
-      T_115181 := enq.bits
+      T_115181 <= enq.bits
       skip
     when do_deq :
       skip
     node T_115184 = neq(do_enq, do_deq)
     when T_115184 :
-      maybe_full := do_enq
+      maybe_full <= do_enq
       skip
     node T_115186 = eq(empty, UInt<1>("h00"))
     node T_115188 = and(UInt<1>("h00"), enq.valid)
     node T_115189 = or(T_115186, T_115188)
-    deq.valid := T_115189
+    deq.valid <= T_115189
     node T_115191 = eq(full, UInt<1>("h00"))
     node T_115193 = and(UInt<1>("h00"), deq.ready)
     node T_115194 = or(T_115191, T_115193)
-    enq.ready := T_115194
+    enq.ready <= T_115194
     infer accessor T_115195 = ram[UInt<1>("h00")]
     wire T_115197 : UInt<17>
-    T_115197 := T_115195
+    T_115197 <= T_115195
     when maybe_flow :
-      T_115197 := enq.bits
+      T_115197 <= enq.bits
       skip
-    deq.bits := T_115197
+    deq.bits <= T_115197
     node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00"))
     node T_115199 = and(maybe_full, ptr_match)
     node T_115200 = T_115199
     node T_115201 = cat(T_115200, ptr_diff)
-    count := T_115201
+    count <= T_115201
     
   module Queue_51 : 
     input clock : Clock
@@ -107,14 +107,14 @@ circuit Top :
     output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}
     output count : UInt<1>
     
-    enq.ready := UInt<1>("h00")
-    deq.bits := UInt<1>("h00")
-    deq.valid := UInt<1>("h00")
-    count := UInt<1>("h00")
+    enq.ready <= UInt<1>("h00")
+    deq.bits <= UInt<1>("h00")
+    deq.valid <= UInt<1>("h00")
+    count <= UInt<1>("h00")
     
     cmem ram : UInt<17>[1], clock
     reg maybe_full : UInt<1>, clock, reset
-    onreset maybe_full := UInt<1>("h00")
+    onreset maybe_full <= UInt<1>("h00")
     node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00"))
     node T_115235 = eq(maybe_full, UInt<1>("h00"))
     node empty = and(ptr_match, T_115235)
@@ -129,32 +129,32 @@ circuit Top :
     node do_deq = and(T_115245, T_115247)
     when do_enq :
       infer accessor T_115249 = ram[UInt<1>("h00")]
-      T_115249 := enq.bits
+      T_115249 <= enq.bits
       skip
     when do_deq :
       skip
     node T_115252 = neq(do_enq, do_deq)
     when T_115252 :
-      maybe_full := do_enq
+      maybe_full <= do_enq
       skip
     node T_115254 = eq(empty, UInt<1>("h00"))
     node T_115256 = and(UInt<1>("h00"), enq.valid)
     node T_115257 = or(T_115254, T_115256)
-    deq.valid := T_115257
+    deq.valid <= T_115257
     node T_115259 = eq(full, UInt<1>("h00"))
     node T_115261 = and(UInt<1>("h00"), deq.ready)
     node T_115262 = or(T_115259, T_115261)
-    enq.ready := T_115262
+    enq.ready <= T_115262
     infer accessor T_115263 = ram[UInt<1>("h00")]
     wire T_115265 : UInt<17>
-    T_115265 := T_115263
+    T_115265 <= T_115263
     when maybe_flow :
-      T_115265 := enq.bits
+      T_115265 <= enq.bits
       skip
-    deq.bits := T_115265
+    deq.bits <= T_115265
     node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00"))
     node T_115267 = and(maybe_full, ptr_match)
     node T_115268 = T_115267
     node T_115269 = cat(T_115268, ptr_diff)
-    count := T_115269
+    count <= T_115269
 
diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir
index 349c4298..30132723 100644
--- a/test/passes/expand-whens/reg-dwc.fir
+++ b/test/passes/expand-whens/reg-dwc.fir
@@ -4,10 +4,10 @@ circuit top :
       input clk : Clock
       input reset : UInt<1>
       wire p : UInt
-      p := UInt(1)
+      p <= UInt(1)
       reg r : UInt,clk,reset
       when p :
-         r := UInt(2)
+         r <= UInt(2)
 
 ; CHECK: Expand Whens
 
@@ -15,8 +15,8 @@ circuit top :
 ; CHECK:   module top :
 ; CHECK:     wire p : UInt
 ; CHECK:     reg r : UInt
-; CHECK:     p := UInt("h1")
-; CHECK:     when p : r := UInt("h2")
+; CHECK:     p <= UInt("h1")
+; CHECK:     when p : r <= UInt("h2")
 
 ; CHECK: Finished Expand Whens
 
diff --git a/test/passes/expand-whens/reg-dwoc.fir b/test/passes/expand-whens/reg-dwoc.fir
index 60bd43a8..002f34a5 100644
--- a/test/passes/expand-whens/reg-dwoc.fir
+++ b/test/passes/expand-whens/reg-dwoc.fir
@@ -4,11 +4,11 @@ circuit top :
       input clk : Clock
       input reset : UInt<1>
       wire p : UInt
-      p := UInt(1)
+      p <= UInt(1)
       reg r : UInt,clk,reset
       when p :
-         onreset r := UInt(1)
-         r := UInt(2)
+         onreset r <= UInt(1)
+         r <= UInt(2)
 
 ; CHECK: Expand Whens
 
@@ -16,8 +16,8 @@ circuit top :
 ; CHECK:   module top :
 ; CHECK:     wire p : UInt
 ; CHECK:     reg r : UInt, clk, reset
-; CHECK:     p := UInt("h1")
-; CHECK:     when p : r := mux(reset, UInt("h1"), UInt("h2"))
+; CHECK:     p <= UInt("h1")
+; CHECK:     when p : r <= mux(reset, UInt("h1"), UInt("h2"))
 
 ; CHECK: Finished Expand Whens
 
diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir
index c6439860..33cac75e 100644
--- a/test/passes/expand-whens/reg-wdc.fir
+++ b/test/passes/expand-whens/reg-wdc.fir
@@ -4,10 +4,10 @@ circuit top :
       input clk : Clock
       input reset : UInt<1>
       wire p : UInt
-      p := UInt(1)
+      p <= UInt(1)
       when p :
          reg r : UInt,clk,reset
-         r := UInt(2)
+         r <= UInt(2)
 
 ; CHECK: Expand Whens
 
@@ -15,8 +15,8 @@ circuit top :
 ; CHECK:   module top :
 ; CHECK:     wire p : UInt
 ; CHECK:     reg r : UInt, clk, reset
-; CHECK:     p := UInt("h1")
-; CHECK-NOT: when p : r := UInt("h2")
+; CHECK:     p <= UInt("h1")
+; CHECK-NOT: when p : r <= UInt("h2")
 
 ; CHECK: Finished Expand Whens
 
diff --git a/test/passes/expand-whens/reg-wdoc.fir b/test/passes/expand-whens/reg-wdoc.fir
index de0bbfd6..1d535aca 100644
--- a/test/passes/expand-whens/reg-wdoc.fir
+++ b/test/passes/expand-whens/reg-wdoc.fir
@@ -4,11 +4,11 @@ circuit top :
       input clk : Clock
       input reset : UInt<1>
       wire p : UInt
-      p := UInt(1)
+      p <= UInt(1)
       when p :
          reg r : UInt,clk,reset
-         onreset r := UInt(1)
-         r := UInt(2)
+         onreset r <= UInt(1)
+         r <= UInt(2)
 
 ; CHECK: Expand Whens
 
@@ -16,8 +16,8 @@ circuit top :
 ; CHECK:   module top :
 ; CHECK:     wire p : UInt
 ; CHECK:     reg r : UInt, clk, reset
-; CHECK:     p := UInt("h1")
-; CHECK-NOT:  when p : r := mux(reset, UInt("h1"), UInt("h2"))
+; CHECK:     p <= UInt("h1")
+; CHECK-NOT:  when p : r <= mux(reset, UInt("h1"), UInt("h2"))
 
 ; CHECK: Finished Expand Whens
 
diff --git a/test/passes/expand-whens/scoped-reg.fir b/test/passes/expand-whens/scoped-reg.fir
index 493d8c41..edce1e1e 100644
--- a/test/passes/expand-whens/scoped-reg.fir
+++ b/test/passes/expand-whens/scoped-reg.fir
@@ -4,11 +4,11 @@ circuit top :
       input clk : Clock
       input reset : UInt<1>
       wire p : UInt
-      p := UInt(1)
+      p <= UInt(1)
       when p :
          reg r : UInt, clk, reset
-         onreset r := UInt(1)
-         r := UInt(2)
+         onreset r <= UInt(1)
+         r <= UInt(2)
 
 ; CHECK: Expand Whens
 
@@ -16,6 +16,6 @@ circuit top :
 ; CHECK:   module top :
 ; CHECK:   wire p : UInt
 ; CHECK:   reg r : UInt, clk, reset
-; CHECK-NOT:  when p : r := mux(reset, UInt("h00000001"), UInt("h00000002"))
+; CHECK-NOT:  when p : r <= mux(reset, UInt("h00000001"), UInt("h00000002"))
 
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir
index 939fac09..05179cf5 100644
--- a/test/passes/expand-whens/two-when.fir
+++ b/test/passes/expand-whens/two-when.fir
@@ -6,34 +6,34 @@ circuit top :
       input clk : Clock
       cmem m :{ x : UInt<1>, y : UInt<1> }[2], clk
       wire i : UInt<1>
-      i := UInt(1)
+      i <= UInt(1)
       wire p : UInt<1>
-      p := UInt(1)
+      p <= UInt(1)
       wire q : { x : UInt<1>, y : UInt<1> }
       when p :
         wire p2 : UInt<1>
-        p2 := UInt(1)
+        p2 <= UInt(1)
         when p2 :
           infer accessor a = m[i] 
-          q := a
+          q <= a
           infer accessor b = m[i]
-          b := q
+          b <= q
         else :
           infer accessor c = m[i] 
-          q := c
+          q <= c
           infer accessor d = m[i]
-          d := q
+          d <= q
       else :
         wire p3 : UInt<1>
-        p3 := UInt(1)
+        p3 <= UInt(1)
         when p3 :
           infer accessor w = m[i] 
-          q := w
+          q <= w
           infer accessor x = m[i]
-          x := q
+          x <= q
         else :
           infer accessor y = m[i] 
-          q := y
+          q <= y
           infer accessor z = m[i]
-          z := q
+          z <= q
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/wacc-wdc.fir b/test/passes/expand-whens/wacc-wdc.fir
index 77c5b194..25fcff17 100644
--- a/test/passes/expand-whens/wacc-wdc.fir
+++ b/test/passes/expand-whens/wacc-wdc.fir
@@ -4,10 +4,10 @@ circuit top :
       input clk : Clock
       wire p : UInt
       cmem m : UInt<4>[10], clk
-      p := UInt(1)
+      p <= UInt(1)
       when p :
          write accessor a = m[UInt(3)]
-         a := UInt(2)
+         a <= UInt(2)
 
 ; CHECK: Expand Whens
 
@@ -16,8 +16,8 @@ circuit top :
 ; CHECK:     wire p : UInt
 ; CHECK:     cmem m : UInt<4>[10], clk
 ; CHECK:     write accessor a = m[UInt("h3")]
-; CHECK:     p := UInt("h1")
-; CHECK:     when p : a := UInt("h2")
+; CHECK:     p <= UInt("h1")
+; CHECK:     when p : a <= UInt("h2")
 
 ; CHECK: Finished Expand Whens