diff options
| author | azidar | 2015-09-30 09:28:08 -0700 |
|---|---|---|
| committer | azidar | 2015-09-30 09:28:08 -0700 |
| commit | 4fefd791eed5ede508a7d47a3f21bf7790d05514 (patch) | |
| tree | cd8e2d451037cd6d393ca8c41bb07e8a8fcdfafa /test/passes/expand-whens | |
| parent | 794e5ada06401a79ea5545e80fb7896bd61e9481 (diff) | |
Fixed naming bug where __1 was matching. Caused lots o issues.
Diffstat (limited to 'test/passes/expand-whens')
| -rw-r--r-- | test/passes/expand-whens/reg-and-when.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/passes/expand-whens/reg-and-when.fir b/test/passes/expand-whens/reg-and-when.fir index 9d23acf9..ac678b6d 100644 --- a/test/passes/expand-whens/reg-and-when.fir +++ b/test/passes/expand-whens/reg-and-when.fir @@ -1,5 +1,5 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p cd 2>&1 | tee %s.out ; cat %s.v | FileCheck %s -; CHECK: out_slow_bits <= fromhost_q$deq$valid ? fromhost_q$deq$bits : tohost_q$deq$bits; +; CHECK: out__slow__bits <= fromhost__q$deq$valid ? fromhost__q$deq$bits : tohost__q$deq$bits; circuit Top : module Top : input clock : Clock |