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authorazidar2015-04-23 15:27:43 -0700
committerazidar2015-04-23 15:27:43 -0700
commit3862865b8c70dd21e1a436dd79cfd165bebe5f43 (patch)
treeb8b3521d588d88218b4bf8b0d53534c6a4deca8e /test/passes/expand-whens/two-when.fir
parentaccb511cb37ce595d28bb3feefe5be79bc6ae303 (diff)
Added new parser. Fixed all Tests. Added on-reset to parser, but don't correctly handle it in compiler.
Diffstat (limited to 'test/passes/expand-whens/two-when.fir')
-rw-r--r--test/passes/expand-whens/two-when.fir14
1 files changed, 7 insertions, 7 deletions
diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir
index c2814038..d3adf5f2 100644
--- a/test/passes/expand-whens/two-when.fir
+++ b/test/passes/expand-whens/two-when.fir
@@ -3,13 +3,13 @@
; CHECK: Expand Whens
circuit top :
module top :
- mem m :{ x : UInt(1), y : UInt(1) }[2]
- wire i : UInt(1)
- wire p : UInt(1)
- wire q : { x : UInt(1), y : UInt(1) }
+ mem m :{ x : UInt<1>, y : UInt<1> }[2]
+ wire i : UInt<1>
+ wire p : UInt<1>
+ wire q : { x : UInt<1>, y : UInt<1> }
when p :
- wire p2 : UInt(1)
- reg r5 : UInt(1)
+ wire p2 : UInt<1>
+ reg r5 : UInt<1>
when p2 :
accessor a = m[i]
q := a
@@ -21,7 +21,7 @@ circuit top :
accessor d = m[i]
d := q
else :
- wire p3 : UInt(1)
+ wire p3 : UInt<1>
when p3 :
accessor w = m[i]
q := w