diff options
| author | azidar | 2016-01-31 12:59:31 -0800 |
|---|---|---|
| committer | azidar | 2016-02-09 18:57:06 -0800 |
| commit | e985d47312458459e9ebe42fe99b5a063c08e637 (patch) | |
| tree | d726c711e86d6e948a220a568dcae0a997629d18 /test/passes/expand-whens/reg-wdc.fir | |
| parent | 2bd423fa061fb3e0973fa83e98f2877fd4616746 (diff) | |
Changed stanza output of UInt/SInt to include widths. Made tests match accordingly
Diffstat (limited to 'test/passes/expand-whens/reg-wdc.fir')
| -rw-r--r-- | test/passes/expand-whens/reg-wdc.fir | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir index b19b8bca..6e8e7c04 100644 --- a/test/passes/expand-whens/reg-wdc.fir +++ b/test/passes/expand-whens/reg-wdc.fir @@ -17,9 +17,9 @@ circuit top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt<2>, clk with : ; CHECK: reset => (reset, r) -; CHECK: p <= UInt("h1") -; CHECK-NOT: r <= mux(p, UInt("h2"), r) -; CHECK: r <= UInt("h2") +; CHECK: p <= UInt<1>("h1") +; CHECK-NOT: r <= mux(p, UInt<2>("h2"), r) +; CHECK: r <= UInt<2>("h2") ; CHECK: Finished Expand Whens |