diff options
| author | Adam Izraelevitz | 2016-08-15 10:32:41 -0700 |
|---|---|---|
| committer | GitHub | 2016-08-15 10:32:41 -0700 |
| commit | bebd04c4c68c320b2b72325e348c726dc33beae6 (patch) | |
| tree | 69f6d4da577977cc7ff428b0545bb4735507aad0 /test/passes/expand-whens/reg-wdc.fir | |
| parent | cca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff) | |
Remove stanza (#231)
* Removed stanza implementation/tests.
In the future we can move the stanza tests over, but for now they should
be deleted.
* Added back integration .fir files
* Added Makefile to give Travis hooks
* Added firrtl script (was ignored before)
Diffstat (limited to 'test/passes/expand-whens/reg-wdc.fir')
| -rw-r--r-- | test/passes/expand-whens/reg-wdc.fir | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir deleted file mode 100644 index 6e8e7c04..00000000 --- a/test/passes/expand-whens/reg-wdc.fir +++ /dev/null @@ -1,26 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire p : UInt - p <= UInt(1) - when p : - reg r : UInt,clk with : - reset => (reset,r) - r <= UInt(2) - -; CHECK: Expand Whens - -; CHECK: circuit top : -; CHECK: module top : -; CHECK: wire p : UInt -; CHECK: reg r : UInt<2>, clk with : -; CHECK: reset => (reset, r) -; CHECK: p <= UInt<1>("h1") -; CHECK-NOT: r <= mux(p, UInt<2>("h2"), r) -; CHECK: r <= UInt<2>("h2") - -; CHECK: Finished Expand Whens - -; CHECK: Done! |