diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/passes/expand-whens/reg-wdc.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/passes/expand-whens/reg-wdc.fir')
| -rw-r--r-- | test/passes/expand-whens/reg-wdc.fir | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir index c6439860..33cac75e 100644 --- a/test/passes/expand-whens/reg-wdc.fir +++ b/test/passes/expand-whens/reg-wdc.fir @@ -4,10 +4,10 @@ circuit top : input clk : Clock input reset : UInt<1> wire p : UInt - p := UInt(1) + p <= UInt(1) when p : reg r : UInt,clk,reset - r := UInt(2) + r <= UInt(2) ; CHECK: Expand Whens @@ -15,8 +15,8 @@ circuit top : ; CHECK: module top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt, clk, reset -; CHECK: p := UInt("h1") -; CHECK-NOT: when p : r := UInt("h2") +; CHECK: p <= UInt("h1") +; CHECK-NOT: when p : r <= UInt("h2") ; CHECK: Finished Expand Whens |