diff options
| author | azidar | 2015-12-12 14:37:41 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | 28e4c6a09011cafdd1e3533118f7c3499e0d3dc6 (patch) | |
| tree | 42e8e2ed50a254f7fea61bc0a56d963258463bb5 /test/passes/expand-whens/reg-wdc.fir | |
| parent | d9f33f58c94382dfbd22e87e2f85600b9807328f (diff) | |
WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadblock in assigning clocked ports
Diffstat (limited to 'test/passes/expand-whens/reg-wdc.fir')
| -rw-r--r-- | test/passes/expand-whens/reg-wdc.fir | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir index 33cac75e..4ddea427 100644 --- a/test/passes/expand-whens/reg-wdc.fir +++ b/test/passes/expand-whens/reg-wdc.fir @@ -6,7 +6,7 @@ circuit top : wire p : UInt p <= UInt(1) when p : - reg r : UInt,clk,reset + reg r : UInt,clk,reset,r r <= UInt(2) ; CHECK: Expand Whens @@ -14,9 +14,10 @@ circuit top : ; CHECK: circuit top : ; CHECK: module top : ; CHECK: wire p : UInt -; CHECK: reg r : UInt, clk, reset +; CHECK: reg r : UInt<2>, clk, reset, r ; CHECK: p <= UInt("h1") -; CHECK-NOT: when p : r <= UInt("h2") +; CHECK-NOT: r <= mux(p, UInt("h2"), r) +; CHECK: r <= UInt("h2") ; CHECK: Finished Expand Whens |