Remove stanza (#231)

* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)

1 files changed, 0 insertions, 33 deletions

diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir
deleted file mode 100644
index 68409931..00000000
--- a/test/passes/expand-whens/nested-whens.fir
+++ /dev/null
@@ -1,33 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; CHECK: Expand Whens
-circuit top :
-   module top :
-      input clk : Clock
-      input reset : UInt<1>
-      wire p : UInt
-      wire q : UInt
-      wire a : UInt
-      wire b : UInt
-      wire x : UInt
-      wire y : UInt
-      wire z : UInt
-      wire w : UInt
-      reg r : UInt, clk with :
-         reset => (reset, w)
-      p <= UInt(1)
-      q <= UInt(1)
-      a <= UInt(1)
-      b <= UInt(1)
-      x <= UInt(1)
-      y <= UInt(1)
-      z <= UInt(1)
-      w <= UInt(1)
-
-      when p :
-        r <= a
-      when q :
-        r <= b
-      r <= z
-; CHECK: r <= z
-; CHECK: Finished Expand Whens
-; CHECK: Done!