New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

1 files changed, 15 insertions, 15 deletions

diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir
index f5f33af6..0a45dac1 100644
--- a/test/passes/expand-whens/nested-whens.fir
+++ b/test/passes/expand-whens/nested-whens.fir
@@ -13,22 +13,22 @@ circuit top :
       wire y : UInt
       wire z : UInt
       wire w : UInt
-      p := UInt(1)
-      q := UInt(1)
-      a := UInt(1)
-      b := UInt(1)
-      x := UInt(1)
-      y := UInt(1)
-      z := UInt(1)
-      w := UInt(1)
+      p <= UInt(1)
+      q <= UInt(1)
+      a <= UInt(1)
+      b <= UInt(1)
+      x <= UInt(1)
+      y <= UInt(1)
+      z <= UInt(1)
+      w <= UInt(1)
 
-      onreset r := w
+      onreset r <= w
       when p :
-        onreset r := x
-        r := a
+        onreset r <= x
+        r <= a
       when q :
-        onreset r := y
-        r := b
-      r := z
-; CHECK: r := mux(reset, mux(q, y, mux(p, x, w)), z)
+        onreset r <= y
+        r <= b
+      r <= z
+; CHECK: r <= mux(reset, mux(q, y, mux(p, x, w)), z)
 ; CHECK: Finished Expand Whens