diff options
| author | azidar | 2016-01-26 14:18:34 -0800 |
|---|---|---|
| committer | azidar | 2016-01-28 09:25:04 -0800 |
| commit | 5ab30c681558d2a26000696e518ee5b28deb1303 (patch) | |
| tree | dcdfaeb3bcb42561e010928712218c8cd3a1b2c7 /test/passes/expand-whens/bundle-init.fir | |
| parent | 8c288f7b159b3f4ca1cb0d5c5012eb8fb52d5214 (diff) | |
Updated all tests to pass
Diffstat (limited to 'test/passes/expand-whens/bundle-init.fir')
| -rw-r--r-- | test/passes/expand-whens/bundle-init.fir | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir index c4b9f314..f4ae9f6a 100644 --- a/test/passes/expand-whens/bundle-init.fir +++ b/test/passes/expand-whens/bundle-init.fir @@ -5,7 +5,8 @@ circuit top : input clk : Clock input reset : UInt<1> wire w : { x : UInt, y : UInt} - reg r : { x : UInt, y : UInt},clk,reset,w + reg r : { x : UInt, y : UInt},clk with : + reset => (reset,w) wire a : UInt wire b : UInt a <= UInt(1) |