diff options
| author | azidar | 2015-03-23 16:12:38 -0700 |
|---|---|---|
| committer | azidar | 2015-03-23 16:12:38 -0700 |
| commit | 3e6d0e2b290aeb49aa9085b75b8a6c57fe1af28c (patch) | |
| tree | b99b309fed9b01210db1754f7148db915334c867 /test/passes/expand-connect-indexed | |
| parent | c61accd4f1c46fa24cf7354d6326141950d827c8 (diff) | |
Finished first two parts of expand-whens pass. Fixed inits by adding WRegInit and removing Null and initialize-register pass
Diffstat (limited to 'test/passes/expand-connect-indexed')
| -rw-r--r-- | test/passes/expand-connect-indexed/bundle-vecs.fir | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir new file mode 100644 index 00000000..ce14c7ba --- /dev/null +++ b/test/passes/expand-connect-indexed/bundle-vecs.fir @@ -0,0 +1,27 @@ +; RUN: firrtl %s abcdefghi c | tee %s.out | FileCheck %s + +; CHECK: Expand Indexed Connects +circuit top : + module q : + wire i : UInt + wire j : UInt + + wire a : { x : UInt(32), flip y : UInt(32) }[2] + ; CHECK: wire a#0#x : UInt(32) + ; CHECK: wire a#0#y : UInt(32) + ; CHECK: wire a#1#x : UInt(32) + ; CHECK: wire a#1#y : UInt(32) + + accessor b = a[i] + ; CHECK: wire b#x : UInt(32) + ; CHECK: wire b#y : UInt(32) + ; CHECK: b#x := a#0#x + ; CHECK: when equal-uu(i, UInt(1)) : + ; CHECK: b#x := a#1#x + ; CHECK: a#0#y := b#y + ; CHECK: when equal-uu(i, UInt(1)) : + ; CHECK: a#1#y := b#y + j := b + +; CHECK: Finished Expand Indexed Connects + |