diff options
| author | jackbackrack | 2015-06-02 08:47:40 -0700 |
|---|---|---|
| committer | jackbackrack | 2015-06-02 08:47:40 -0700 |
| commit | b178ca42fd9d4f7b94d80c01cd810bf18da9ebc8 (patch) | |
| tree | 033e197aa2e297187e21712faf1957eb405b435b /test/passes/expand-connect-indexed/bundle-vecs.fir | |
| parent | e668a13b285c87678a708a8af5bee2cfa0f7645b (diff) | |
| parent | 8fc826a2770f46d63d8d7b1bccf14d2bf6e6b7cd (diff) | |
merge + fix trim to use correct bits operands
Diffstat (limited to 'test/passes/expand-connect-indexed/bundle-vecs.fir')
| -rw-r--r-- | test/passes/expand-connect-indexed/bundle-vecs.fir | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir index 901ab4e6..9d375087 100644 --- a/test/passes/expand-connect-indexed/bundle-vecs.fir +++ b/test/passes/expand-connect-indexed/bundle-vecs.fir @@ -7,23 +7,23 @@ circuit top : wire j : UInt wire a : { x : UInt<32>, flip y : UInt<32> }[2] - ; CHECK: wire a_0_x : UInt<32> - ; CHECK: wire a_0_y : UInt<32> - ; CHECK: wire a_1_x : UInt<32> - ; CHECK: wire a_1_y : UInt<32> + ; CHECK: wire a$0$x : UInt<32> + ; CHECK: wire a$0$y : UInt<32> + ; CHECK: wire a$1$x : UInt<32> + ; CHECK: wire a$1$y : UInt<32> accessor b = a[i] - ; CHECK: wire b_x : UInt<32> - ; CHECK: wire b_y : UInt<32> - ; CHECK: b_x := a_0_x - ; CHECK: node b_x__0 = i - ; CHECK: when eq(b_x__0, UInt(1)) : - ; CHECK: b_x := a_1_x - ; CHECK: node b_y__0 = i - ; CHECK: when eq(b_y__0, UInt(0)) : - ; CHECK: a_0_y := b_y - ; CHECK: when eq(b_y__0, UInt(1)) : - ; CHECK: a_1_y := b_y + ; CHECK: wire b$x : UInt<32> + ; CHECK: wire b$y : UInt<32> + ; CHECK: b$x := a$0$x + ; CHECK: node i#0 = i + ; CHECK: when eq(i#0, UInt(1)) : + ; CHECK: b$x := a$1$x + ; CHECK: node i#1 = i + ; CHECK: when eq(i#1, UInt(0)) : + ; CHECK: a$0$y := b$y + ; CHECK: when eq(i#1, UInt(1)) : + ; CHECK: a$1$y := b$y j := b.x ; CHECK: Finished Expand Indexed Connects |