diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/passes/const-prop/rsh.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/passes/const-prop/rsh.fir')
| -rw-r--r-- | test/passes/const-prop/rsh.fir | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/passes/const-prop/rsh.fir b/test/passes/const-prop/rsh.fir index 8c13e410..4159899f 100644 --- a/test/passes/const-prop/rsh.fir +++ b/test/passes/const-prop/rsh.fir @@ -1,14 +1,14 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s ;CHECK: Constant Propagation -;CHECK: x := UInt("h1f") -;CHECK: y := SInt("h20") +;CHECK: x <= UInt("h1f") +;CHECK: y <= SInt("h20") ;CHECK: Finished Constant Propagation circuit top : module top : output x : UInt output y : SInt - x := shr(UInt(127),2) - y := shr(SInt(-128),2) + x <= shr(UInt(127),2) + y <= shr(SInt(-128),2) |