diff options
| author | Adam Izraelevitz | 2016-08-15 10:32:41 -0700 |
|---|---|---|
| committer | GitHub | 2016-08-15 10:32:41 -0700 |
| commit | bebd04c4c68c320b2b72325e348c726dc33beae6 (patch) | |
| tree | 69f6d4da577977cc7ff428b0545bb4735507aad0 /test/features/VerilogRename.fir | |
| parent | cca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff) | |
Remove stanza (#231)
* Removed stanza implementation/tests.
In the future we can move the stanza tests over, but for now they should
be deleted.
* Added back integration .fir files
* Added Makefile to give Travis hooks
* Added firrtl script (was ignored before)
Diffstat (limited to 'test/features/VerilogRename.fir')
| -rw-r--r-- | test/features/VerilogRename.fir | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/test/features/VerilogRename.fir b/test/features/VerilogRename.fir deleted file mode 100644 index f8fceaa9..00000000 --- a/test/features/VerilogRename.fir +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -circuit Top : - module Top : - input with : Clock - output unsigned : Clock - wire trireg : Clock - unsigned <= with - trireg <= with - -;CHECK: Verilog Rename - -;CHECK: input with$ : Clock -;CHECK: output unsigned$ : Clock -;CHECK: wire trireg$ : Clock -;CHECK: trireg$ <= with$ -;CHECK: unsigned$ <= with$ - -;CHECK: Done! |