diff options
| author | Adam Izraelevitz | 2016-08-15 10:32:41 -0700 |
|---|---|---|
| committer | GitHub | 2016-08-15 10:32:41 -0700 |
| commit | bebd04c4c68c320b2b72325e348c726dc33beae6 (patch) | |
| tree | 69f6d4da577977cc7ff428b0545bb4735507aad0 /test/features/VerilogReg.fir | |
| parent | cca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff) | |
Remove stanza (#231)
* Removed stanza implementation/tests.
In the future we can move the stanza tests over, but for now they should
be deleted.
* Added back integration .fir files
* Added Makefile to give Travis hooks
* Added firrtl script (was ignored before)
Diffstat (limited to 'test/features/VerilogReg.fir')
| -rw-r--r-- | test/features/VerilogReg.fir | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/test/features/VerilogReg.fir b/test/features/VerilogReg.fir deleted file mode 100644 index 96022933..00000000 --- a/test/features/VerilogReg.fir +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Done! -circuit Poison : - module Poison : - input clk : Clock - input reset : UInt<1> - input p1 : UInt<1> - input p2 : UInt<1> - input p3 : UInt<1> - reg r : UInt<32>,clk with : - reset => (reset,r) - when p1 : - r <= UInt(1) - when p2 : - r <= UInt(2) - when p3 : - r <= UInt(3) - |