diff options
| author | azidar | 2016-01-26 14:18:34 -0800 |
|---|---|---|
| committer | azidar | 2016-01-28 09:25:04 -0800 |
| commit | 5ab30c681558d2a26000696e518ee5b28deb1303 (patch) | |
| tree | dcdfaeb3bcb42561e010928712218c8cd3a1b2c7 /test/features/VerilogReg.fir | |
| parent | 8c288f7b159b3f4ca1cb0d5c5012eb8fb52d5214 (diff) | |
Updated all tests to pass
Diffstat (limited to 'test/features/VerilogReg.fir')
| -rw-r--r-- | test/features/VerilogReg.fir | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/test/features/VerilogReg.fir b/test/features/VerilogReg.fir index 33c4417f..96022933 100644 --- a/test/features/VerilogReg.fir +++ b/test/features/VerilogReg.fir @@ -7,7 +7,8 @@ circuit Poison : input p1 : UInt<1> input p2 : UInt<1> input p3 : UInt<1> - reg r : UInt<32>,clk,reset,r + reg r : UInt<32>,clk with : + reset => (reset,r) when p1 : r <= UInt(1) when p2 : |