Updated all tests to pass

1 files changed, 9 insertions, 5 deletions

diff --git a/test/features/TwoClocks.fir b/test/features/TwoClocks.fir
index 6562d3e1..3753ee8d 100644
--- a/test/features/TwoClocks.fir
+++ b/test/features/TwoClocks.fir
@@ -5,14 +5,18 @@ circuit Top :
     input clk2 : Clock
     input reset1 : UInt<1>
     input reset2 : UInt<1>
-    reg src : UInt<10>, clk1, reset1, UInt(0)
-    reg sink : UInt<10>, clk2, reset2, UInt(0)
+    reg src : UInt<10>, clk1 with :
+       reset => ( reset1, UInt(0))
+    reg sink : UInt<10>, clk2 with :
+       reset => ( reset2, UInt(0))
 
-    src <= addw(src,UInt(1))
+    src <= add(src,UInt(1))
 
-    reg sync_A : UInt<10>, clk2, reset2, UInt(0)
+    reg sync_A : UInt<10>, clk2 with :
+       reset => ( reset2, UInt(0))
     sync_A <= src
-    reg sync_B : UInt<10>, clk2, reset2, UInt(0)
+    reg sync_B : UInt<10>, clk2 with :
+       reset => ( reset2, UInt(0))
     sync_B <= sync_A
 
     sink <= sync_B