New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

1 files changed, 6 insertions, 6 deletions

diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir
index 9690f2d1..354bd8de 100644
--- a/test/features/SeqMem.fir
+++ b/test/features/SeqMem.fir
@@ -4,21 +4,21 @@ circuit Top :
   module Top : 
     input clk : Clock
     wire i : UInt<5>
-    i := UInt(1)
+    i <= UInt(1)
     wire i0 : UInt<5>
     wire j : UInt<128>
 
-    i0 := UInt(10)
+    i0 <= UInt(10)
 
     cmem m-com : UInt<128>[32], clk
     infer accessor r-com = m-com[i]
     infer accessor w-com = m-com[i]
-    j := r-com
-    w-com := j
+    j <= r-com
+    w-com <= j
 
 
     smem m-seq : UInt<128>[32], clk
     infer accessor r-seq = m-seq[i]
     infer accessor w-seq = m-seq[i]
-    j := r-seq
-    w-seq := j
+    j <= r-seq
+    w-seq <= j