Added sequential memories. mem no longer exists, must declare either cmem or smem. Added firrtl-gensym utility to generate a hashmap of names

1 files changed, 22 insertions, 0 deletions

diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir
new file mode 100644
index 00000000..998df8c9
--- /dev/null
+++ b/test/features/SeqMem.fir
@@ -0,0 +1,22 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+circuit Top : 
+  module Top : 
+    wire i : UInt<5>
+    wire i0 : UInt<5>
+    wire j : UInt<128>
+
+    i0 := UInt(10)
+
+    cmem m-com : UInt<128>[32]
+    accessor r-com = m-com[i]
+    accessor w-com = m-com[i]
+    j := r-com
+    w-com := j
+
+
+    smem m-seq : UInt<128>[32]
+    accessor r-seq = m-seq[i]
+    accessor w-seq = m-seq[i]
+    j := r-seq
+    w-seq := j