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authorazidar2016-01-28 12:12:02 -0800
committerazidar2016-01-28 12:12:02 -0800
commit9ed79a822f7f406c55af8082da04cb7739e772eb (patch)
tree02b10696dd0a03faf54c8eafa046855ccfc26e8f /test/features/Queue.fir
parentb7dcc8ccbb1459a604353a8137081a9b156d276e (diff)
parent094c6b8e7b40a3c613547d6127b449d0b1503db3 (diff)
Merge branch 'new-reg-prims' of github.com:ucb-bar/firrtl
Diffstat (limited to 'test/features/Queue.fir')
-rw-r--r--test/features/Queue.fir3
1 files changed, 2 insertions, 1 deletions
diff --git a/test/features/Queue.fir b/test/features/Queue.fir
index 9b19caf4..3ce58e31 100644
--- a/test/features/Queue.fir
+++ b/test/features/Queue.fir
@@ -7,6 +7,7 @@ circuit Queue :
input clk : Clock
input reset : UInt<1>
- reg r : UInt<10>,clk,reset,in
+ reg r : UInt<10>,clk with :
+ reset => (reset,in)
r <= in
out <= r