New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

1 files changed, 10 insertions, 9 deletions

diff --git a/test/features/Printf.fir b/test/features/Printf.fir
index 2f8dc985..4e8682ff 100644
--- a/test/features/Printf.fir
+++ b/test/features/Printf.fir
@@ -1,20 +1,21 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
 
-;CHECK: Lower To Ground
+;CHECK: Expand Whens
 circuit Top : 
   module Top : 
     input x : {y : UInt<1>}
     input p : UInt<1>
     input clk : Clock
-    printf(clk,"Hello World!\n")
-    printf(clk,"Hello World! %x\n", x.y)
+    input en : UInt<1>
+    printf(clk,en,"Hello World!\n")
+    printf(clk,en,"Hello World! %x\n", x.y)
     when p :
-       printf(clk,"In consequence\n")
+       printf(clk,en,"In consequence\n")
     else :
-       printf(clk,"In alternate\n")
+       printf(clk,en,"In alternate\n")
 
-;CHECK: printf(clk, "Hello World!\n")
-;CHECK: printf(clk, "Hello World! %x\n", x$y)
-;CHECK: when p : printf(clk, "In consequence\n")
-;CHECK: when not(p) : printf(clk, "In alternate\n")   
+;CHECK: printf(clk, en, "Hello World!\n")
+;CHECK: printf(clk, en, "Hello World! %x\n", x.y)
+;CHECK: printf(clk, and(p, en), "In consequence\n")
+;CHECK: printf(clk, and(eqv(p, UInt("h0")), en), "In alternate\n")   
 ;CHECK: Done!