Merge branch 'new-reg-prims' of github.com:ucb-bar/firrtl

1 files changed, 17 insertions, 0 deletions

diff --git a/test/features/OptionalRegisterReset.fir b/test/features/OptionalRegisterReset.fir
new file mode 100644
index 00000000..54a90b67
--- /dev/null
+++ b/test/features/OptionalRegisterReset.fir
@@ -0,0 +1,17 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+circuit Top : 
+  module Top : 
+    input clk : Clock
+    input reset : UInt<1>
+    input a : UInt<32>
+    input p : UInt<1>
+    output b : UInt<32>
+    reg r1:UInt<32> clk with : 
+      reset => (reset, a)
+    when p :
+      b <= r1
+    else :
+      b <= r1
+
+
+;CHECK: Done!