diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/features/Long.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/features/Long.fir')
| -rw-r--r-- | test/features/Long.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/features/Long.fir b/test/features/Long.fir index b191ac55..7ac5ad6c 100644 --- a/test/features/Long.fir +++ b/test/features/Long.fir @@ -3,4 +3,4 @@ circuit Top : module Top : wire a : UInt - a := UInt("h4261441663") + a <= UInt("h4261441663") |