Updated error and feature tests. Fixed bug in detecting incorrect genders

1 files changed, 21 insertions, 0 deletions

diff --git a/test/features/InitializeVec.fir b/test/features/InitializeVec.fir
new file mode 100644
index 00000000..30c59fb9
--- /dev/null
+++ b/test/features/InitializeVec.fir
@@ -0,0 +1,21 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+circuit Tst : 
+  module Tst : 
+    output in : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>}
+    output outs : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>}[4]
+    
+    in.ready := UInt<1>(1)
+    outs[0].valid := UInt<1>(0)
+    outs[0].bits := UInt<1>(0)
+    outs[1].valid := UInt<1>(0)
+    outs[1].bits := UInt<1>(0)
+    outs[2].valid := UInt<1>(0)
+    outs[2].bits := UInt<1>(0)
+    outs[3].valid := UInt<1>(0)
+    outs[3].bits := UInt<1>(0)
+    in.ready := UInt<1>(1)
+    infer accessor out = outs[in.bits]
+    when out.ready : 
+      out.bits := UInt<7>(99)
+      out.valid := UInt<1>(1)