diff options
| author | azidar | 2015-12-10 12:27:56 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | 0246ab2479724fb0118bb7a25577c71e2a038223 (patch) | |
| tree | e3a5aa22a3712d28b5b094580cd50babd6520e2f /test/features/InitializeVec.fir | |
| parent | be78d49aa01c097978f69a3b022acb2047fdf438 (diff) | |
WIP, hit semantic bug in WSubAccess
Diffstat (limited to 'test/features/InitializeVec.fir')
| -rw-r--r-- | test/features/InitializeVec.fir | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/test/features/InitializeVec.fir b/test/features/InitializeVec.fir index ef6400a0..1cc44daf 100644 --- a/test/features/InitializeVec.fir +++ b/test/features/InitializeVec.fir @@ -1,5 +1,5 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * + ;CHECK: Done! circuit Tst : module Tst : @@ -16,7 +16,6 @@ circuit Tst : outs[3].valid <= UInt<1>(0) outs[3].bits <= UInt<1>(0) in.ready <= UInt<1>(1) - infer accessor out = outs[in.bits] - when out.ready : - out.bits <= UInt<7>(99) - out.valid <= UInt<1>(1) + when outs[in.bits].ready : + outs[in.bits].bits <= UInt<7>(99) + outs[in.bits].valid <= UInt<1>(1) |