diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/features/InitAccessor.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/features/InitAccessor.fir')
| -rw-r--r-- | test/features/InitAccessor.fir | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/features/InitAccessor.fir b/test/features/InitAccessor.fir index 0bf861f2..356b5a68 100644 --- a/test/features/InitAccessor.fir +++ b/test/features/InitAccessor.fir @@ -5,10 +5,10 @@ circuit Top : module Top : input in : UInt<1> wire b : UInt<1>[3] - b.0 := UInt(1) - b.1 := UInt(1) - b.2 := UInt(1) + b.0 <= UInt(1) + b.1 <= UInt(1) + b.2 <= UInt(1) node c = UInt(1) infer accessor a = b[c] when in : - a := UInt(1) + a <= UInt(1) |