diff options
| author | azidar | 2015-12-10 19:32:43 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | 5dfed8b731764834e4d16197d4f8c31f16daff75 (patch) | |
| tree | ad407f410e590700e4bf38312cf2acbd0d59f9ed /test/features/InitAccessor.fir | |
| parent | 0246ab2479724fb0118bb7a25577c71e2a038223 (diff) | |
Finished supporting nested accesses. Required some nuianced thinking. Pass all feature tests. Deleted CondRead because it tested a problem we don't have any more
Diffstat (limited to 'test/features/InitAccessor.fir')
| -rw-r--r-- | test/features/InitAccessor.fir | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/test/features/InitAccessor.fir b/test/features/InitAccessor.fir index 356b5a68..5a81a62e 100644 --- a/test/features/InitAccessor.fir +++ b/test/features/InitAccessor.fir @@ -1,14 +1,13 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * + ;CHECK: Done! circuit Top : module Top : input in : UInt<1> wire b : UInt<1>[3] - b.0 <= UInt(1) - b.1 <= UInt(1) - b.2 <= UInt(1) + b[0] <= UInt(1) + b[1] <= UInt(1) + b[2] <= UInt(1) node c = UInt(1) - infer accessor a = b[c] when in : - a <= UInt(1) + b[c] <= UInt(1) |