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authorazidar2015-12-12 14:37:41 -0800
committerazidar2016-01-16 14:28:17 -0800
commit28e4c6a09011cafdd1e3533118f7c3499e0d3dc6 (patch)
tree42e8e2ed50a254f7fea61bc0a56d963258463bb5 /test/features/BulkConnect.fir
parentd9f33f58c94382dfbd22e87e2f85600b9807328f (diff)
WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadblock in assigning clocked ports
Diffstat (limited to 'test/features/BulkConnect.fir')
-rw-r--r--test/features/BulkConnect.fir2
1 files changed, 1 insertions, 1 deletions
diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir
index a57ce199..1b68bbdc 100644
--- a/test/features/BulkConnect.fir
+++ b/test/features/BulkConnect.fir
@@ -2,7 +2,7 @@
;CHECK: Expand Connects
circuit Top :
module Top :
- wire a : { w : UInt<42>}
+ wire a : { w : UInt}
a.w <= UInt(1)
wire b : { w : UInt<42>, x : UInt<20>}
b.w <= UInt(1)