diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/features/BigInt.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/features/BigInt.fir')
| -rw-r--r-- | test/features/BigInt.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/features/BigInt.fir b/test/features/BigInt.fir index 225f1d8b..a8dadcfc 100644 --- a/test/features/BigInt.fir +++ b/test/features/BigInt.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s circuit Top : module Top : node x = UInt("h2") |