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authorazidar2015-07-13 16:22:43 -0700
committerazidar2015-07-14 11:29:55 -0700
commit271e1bf5ed56847c1ce7d50bdb7f1db9ccc5ea55 (patch)
tree8b1cdfcfc97a9710bd1bc5be973578f712cfa253 /test/errors/high-form/SpecialChars.fir
parent0bfb3618b654a4082cc2780887b3ca32e374f455 (diff)
Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass
Diffstat (limited to 'test/errors/high-form/SpecialChars.fir')
-rw-r--r--test/errors/high-form/SpecialChars.fir35
1 files changed, 35 insertions, 0 deletions
diff --git a/test/errors/high-form/SpecialChars.fir b/test/errors/high-form/SpecialChars.fir
new file mode 100644
index 00000000..f224ce68
--- /dev/null
+++ b/test/errors/high-form/SpecialChars.fir
@@ -0,0 +1,35 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+; CHECK: Done!
+
+circuit Top :
+ module Top :
+ wire x : UInt<1>
+ x := UInt(1)
+ wire x~y : UInt<2>
+ x~y := UInt(1)
+ wire x!y : UInt<2>
+ x!y := UInt(1)
+ wire x@y : UInt<2>
+ x@y := UInt(1)
+ wire x#y : UInt<2>
+ x#y := UInt(1)
+ wire x%y : UInt<2>
+ x%y := UInt(1)
+ wire x^y : UInt<2>
+ x^y := UInt(1)
+ wire x*y : UInt<2>
+ x*y := UInt(1)
+ wire x-y : UInt<2>
+ x-y := UInt(1)
+ wire x_y : UInt<2>
+ x_y := UInt(1)
+ wire x+y : UInt<2>
+ x+y := UInt(1)
+ wire x=y : UInt<2>
+ x=y := UInt(1)
+ wire x?y : UInt<2>
+ x?y := UInt(1)
+ wire x/y : UInt<2>
+ x/y := UInt(1)
+
+