diff options
| author | azidar | 2015-05-20 01:35:15 -0700 |
|---|---|---|
| committer | azidar | 2015-05-20 01:35:15 -0700 |
| commit | ed04a9040f20c5e04880a18ec036c1a641443c50 (patch) | |
| tree | cb9cd4db719484c0a8ea52054915841bc8e0eb14 /test/errors/high-form/InvalidLOC.fir | |
| parent | 92e7da031a14df41ee0cab13a4a63b472fbdb5e1 (diff) | |
Added Pad pass to flo.stanza, which pads widths to make := and primops strict. Have not tested this
Diffstat (limited to 'test/errors/high-form/InvalidLOC.fir')
| -rw-r--r-- | test/errors/high-form/InvalidLOC.fir | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/test/errors/high-form/InvalidLOC.fir b/test/errors/high-form/InvalidLOC.fir index 5270577b..cbbb53a9 100644 --- a/test/errors/high-form/InvalidLOC.fir +++ b/test/errors/high-form/InvalidLOC.fir @@ -1,5 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s -; CHECK: Invalid connect to an expression that is not a reference or a WritePort. +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ; CHECK: Invalid connect to an expression that is not a reference or a WritePort. ; CHECK: Invalid connect to an expression that is not a reference or a WritePort. ; CHECK: Invalid connect to an expression that is not a reference or a WritePort. @@ -10,7 +9,6 @@ circuit Top : module Top : wire x : UInt add(x,x) := UInt(1) - Pad(x,?) := UInt(1) Register(x,x) := UInt(1) ReadPort(x,x,x) := UInt(1) UInt(1) := UInt(1) |