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authorazidar2015-12-09 18:31:45 -0800
committerazidar2016-01-16 14:28:17 -0800
commitbe78d49aa01c097978f69a3b022acb2047fdf438 (patch)
tree76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/errors/gender/InstancePorts.fir
parentc427b31a1ef8361b643d5f7435aeb42472dfe626 (diff)
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
Diffstat (limited to 'test/errors/gender/InstancePorts.fir')
-rw-r--r--test/errors/gender/InstancePorts.fir6
1 files changed, 3 insertions, 3 deletions
diff --git a/test/errors/gender/InstancePorts.fir b/test/errors/gender/InstancePorts.fir
index 55d5fd46..3f5ae8c7 100644
--- a/test/errors/gender/InstancePorts.fir
+++ b/test/errors/gender/InstancePorts.fir
@@ -6,12 +6,12 @@ circuit BTB :
module Queue :
input in : UInt<1>
output out : UInt<1>
- out := in
+ out <= in
module BTB :
input time : UInt<1>
output out : UInt<1>
inst queue of Queue
- queue.in := time
- out := queue.in
+ queue.in <= time
+ out <= queue.in