Removed old chisel3 tests that all failed for syntax reasons. Tests should now be small examples, categorized by either passes, errors, or features.

1 files changed, 0 insertions, 19 deletions

diff --git a/test/chisel3/Tbl.fir b/test/chisel3/Tbl.fir
deleted file mode 100644
index 013fd098..00000000
--- a/test/chisel3/Tbl.fir
+++ /dev/null
@@ -1,19 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
-;CHECK: Done!
-
-circuit Tbl : 
-  module Tbl : 
-    input i : UInt<16>
-    input d : UInt<16>
-    output o : UInt<16>
-    input we : UInt<1>
-    
-    cmem m : UInt<10>[256]
-    o := UInt<1>(0)
-    when we : 
-      infer accessor T_13 = m[i]
-      node T_14 = bits(d, 9, 0)
-      T_13 := T_14
-    else : 
-      infer accessor T_15 = m[i]
-      o := T_15