diff options
| author | azidar | 2015-05-21 13:18:09 -0400 |
|---|---|---|
| committer | azidar | 2015-05-21 13:18:09 -0400 |
| commit | eb125225cb96875f31a9af0db187406782b75223 (patch) | |
| tree | a37566e307424a277a3d2fe229f069cbbcca4ae4 /test/chisel3/Outer.fir | |
| parent | 81905d9fdd0debe8f666658607c2a20728baa86d (diff) | |
Added pad pass, used for flo backend
Diffstat (limited to 'test/chisel3/Outer.fir')
| -rw-r--r-- | test/chisel3/Outer.fir | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/chisel3/Outer.fir b/test/chisel3/Outer.fir index 2e1e4475..a7631277 100644 --- a/test/chisel3/Outer.fir +++ b/test/chisel3/Outer.fir @@ -1,12 +1,12 @@ -; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s -; CHECK: Done! +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +;CHECK: Done! + circuit Outer : module Inner : input in : UInt<8> output out : UInt<8> - node T_14 = UInt<1>(1) - node T_15 = add(in, T_14) + node T_15 = add-wrap(in, UInt<1>(1)) out := T_15 module Outer : input in : UInt<8> @@ -14,6 +14,6 @@ circuit Outer : inst T_16 of Inner T_16.in := in - node T_17 = UInt<2>(2) - node T_18 = mul(T_16.out, T_17) + node T_17 = mul(T_16.out, UInt<2>(2)) + node T_18 = bits(T_17, 7, 0) out := T_18 |