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authorjackbackrack2015-04-28 18:25:40 -0700
committerjackbackrack2015-04-28 18:25:40 -0700
commit4b64107635c702352721a8fbb6ee71a455b9da54 (patch)
treee66da971c5ac7e2866db9371522d07d10b115053 /test/chisel3/Outer.fir
parent2a4f374b19e10a1571fbd2a23b30e92c9179defd (diff)
parentc46608d92bd493fa33c3c5122341c716ca75ecb0 (diff)
merge
Diffstat (limited to 'test/chisel3/Outer.fir')
-rw-r--r--test/chisel3/Outer.fir12
1 files changed, 6 insertions, 6 deletions
diff --git a/test/chisel3/Outer.fir b/test/chisel3/Outer.fir
index 227c5dae..2e1e4475 100644
--- a/test/chisel3/Outer.fir
+++ b/test/chisel3/Outer.fir
@@ -2,18 +2,18 @@
; CHECK: Done!
circuit Outer :
module Inner :
- input in : UInt(8)
- output out : UInt(8)
+ input in : UInt<8>
+ output out : UInt<8>
- node T_14 = UInt(1, 1)
+ node T_14 = UInt<1>(1)
node T_15 = add(in, T_14)
out := T_15
module Outer :
- input in : UInt(8)
- output out : UInt(8)
+ input in : UInt<8>
+ output out : UInt<8>
inst T_16 of Inner
T_16.in := in
- node T_17 = UInt(2, 2)
+ node T_17 = UInt<2>(2)
node T_18 = mul(T_16.out, T_17)
out := T_18