diff options
| author | azidar | 2015-04-28 17:32:19 -0700 |
|---|---|---|
| committer | azidar | 2015-04-28 17:32:19 -0700 |
| commit | 1644ed195522cd7343aaaa047e6669529907de9f (patch) | |
| tree | 250d34e3bf5616e01b4629ee6497cdd1ce9647b8 /test/chisel3/Outer.fir | |
| parent | d6d630e6dbe3e5dd3c335cc8bd65a81d9dcb0f5f (diff) | |
Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec.fir doesn't work because incorrecly generated?
Diffstat (limited to 'test/chisel3/Outer.fir')
| -rw-r--r-- | test/chisel3/Outer.fir | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/chisel3/Outer.fir b/test/chisel3/Outer.fir index 227c5dae..2e1e4475 100644 --- a/test/chisel3/Outer.fir +++ b/test/chisel3/Outer.fir @@ -2,18 +2,18 @@ ; CHECK: Done! circuit Outer : module Inner : - input in : UInt(8) - output out : UInt(8) + input in : UInt<8> + output out : UInt<8> - node T_14 = UInt(1, 1) + node T_14 = UInt<1>(1) node T_15 = add(in, T_14) out := T_15 module Outer : - input in : UInt(8) - output out : UInt(8) + input in : UInt<8> + output out : UInt<8> inst T_16 of Inner T_16.in := in - node T_17 = UInt(2, 2) + node T_17 = UInt<2>(2) node T_18 = mul(T_16.out, T_17) out := T_18 |