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authorazidar2015-04-16 17:05:46 -0700
committerazidar2015-04-16 17:05:46 -0700
commit06ff7f7dddcb479d9d4d775a55cbb18d873b35b9 (patch)
tree5023aa9aa4e944d9b3911a8dddf43ece6f6f1455 /test/chisel3/Mul.fir
parent5dfc741fd04c7fa357b976b57086d67244d3d22a (diff)
Updated parser to correctly read empty statements
Diffstat (limited to 'test/chisel3/Mul.fir')
-rw-r--r--test/chisel3/Mul.fir2
1 files changed, 1 insertions, 1 deletions
diff --git a/test/chisel3/Mul.fir b/test/chisel3/Mul.fir
index f8ba0b78..e41537e3 100644
--- a/test/chisel3/Mul.fir
+++ b/test/chisel3/Mul.fir
@@ -41,4 +41,4 @@ circuit Mul :
node T_61 : UInt(2) = shift-left(x, T_60)
node T_62 : UInt(2) = bit-or(T_61, y)
accessor T_63 = tbl[T_62]
- z := T_63 \ No newline at end of file
+ z := T_63