diff options
| author | azidar | 2015-04-20 12:08:10 -0700 |
|---|---|---|
| committer | azidar | 2015-04-20 12:08:10 -0700 |
| commit | 7617e33993abf9f6be357e0261755a4736c2e085 (patch) | |
| tree | a8a32a3e0d731b49173f1c6f02056aea20902ada /test/chisel3/LFSR16.fir | |
| parent | 130c6676418e85d5d4dd12a0f0845e912eda8c3e (diff) | |
Fixed tests to use new execution arguments. Added and fixed chisel3 bugs
Diffstat (limited to 'test/chisel3/LFSR16.fir')
| -rw-r--r-- | test/chisel3/LFSR16.fir | 24 |
1 files changed, 14 insertions, 10 deletions
diff --git a/test/chisel3/LFSR16.fir b/test/chisel3/LFSR16.fir index 7d1d6073..a8857882 100644 --- a/test/chisel3/LFSR16.fir +++ b/test/chisel3/LFSR16.fir @@ -1,20 +1,24 @@ +; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s +; CHECK: Done! + circuit LFSR16 : module LFSR16 : output out : UInt(16) input inc : UInt(1) - node T_16 : UInt(16) = UInt(1, 16) + node T_16 = UInt(1, 16) reg res : UInt(16) res.init := T_16 when inc : - node T_17 : UInt(1) = bit(res, 0) - node T_18 : UInt(1) = bit(res, 2) - node T_19 : UInt(1) = bit-xor(T_17, T_18) - node T_20 : UInt(1) = bit(res, 3) - node T_21 : UInt(1) = bit-xor(T_19, T_20) - node T_22 : UInt(1) = bit(res, 5) - node T_23 : UInt(1) = bit-xor(T_21, T_22) - node T_24 : UInt = bits(res, 15, 1) - node T_25 : UInt(1) = concat(T_23, T_24) + node T_17 = bit(res, 0) + node T_18 = bit(res, 2) + node T_19 = bit-xor(T_17, T_18) + node T_20 = bit(res, 3) + node T_21 = bit-xor(T_19, T_20) + node T_22 = bit(res, 5) + node T_23 = bit-xor(T_21, T_22) + node T_24 = bits(res, 15, 1) + node T_25 = cat(T_23, T_24) res := T_25 out := res + |