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authorazidar2015-05-26 17:33:40 -0700
committerazidar2015-05-26 17:33:40 -0700
commitcf80ff9c83c2fedd42ec186a3e342520c89f91ab (patch)
treeebbf3455b91e8840d49057754585d567dacea384 /test/chisel3/GCD.fir
parenteb125225cb96875f31a9af0db187406782b75223 (diff)
Added <>. Added additional checks for primops. Added new chisel3 files.
Diffstat (limited to 'test/chisel3/GCD.fir')
-rw-r--r--test/chisel3/GCD.fir26
1 files changed, 26 insertions, 0 deletions
diff --git a/test/chisel3/GCD.fir b/test/chisel3/GCD.fir
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+++ b/test/chisel3/GCD.fir
@@ -0,0 +1,26 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
+circuit GCD :
+ module GCD :
+ output v : UInt<1>
+ input e : UInt<1>
+ output z : UInt<16>
+ input a : UInt<16>
+ input b : UInt<16>
+
+ reg x : UInt<16>
+ reg y : UInt<16>
+ node T_17 = gt(x, y)
+ when T_17 :
+ node T_18 = sub-wrap(x, y)
+ x := T_18
+ else :
+ node T_19 = sub-wrap(y, x)
+ y := T_19
+ when e :
+ x := a
+ y := b
+ z := x
+ node T_20 = eq(y, UInt<1>(0))
+ v := T_20