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authorazidar2015-07-10 13:25:21 -0700
committerazidar2015-07-14 11:29:55 -0700
commit0bfb3618b654a4082cc2780887b3ca32e374f455 (patch)
tree230b7cbc96589be229e6f3d87f21300fb8fd84c3 /test/chisel3/ALUTop.fir
parent0d63d521de85d1c6b9109e019101d0f575d063f7 (diff)
Added clock support
Diffstat (limited to 'test/chisel3/ALUTop.fir')
-rw-r--r--test/chisel3/ALUTop.fir28
1 files changed, 14 insertions, 14 deletions
diff --git a/test/chisel3/ALUTop.fir b/test/chisel3/ALUTop.fir
index a6fdfd95..df7235b7 100644
--- a/test/chisel3/ALUTop.fir
+++ b/test/chisel3/ALUTop.fir
@@ -1,5 +1,5 @@
; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
-;CHECK: Done!
+; CHECK: Done!
circuit ALUTop :
module ALU :
@@ -10,23 +10,23 @@ circuit ALUTop :
input alu_op : UInt<4>
node shamt = bits(B, 4, 0)
- node T_157 = add-wrap(A, B)
- node T_158 = sub-wrap(A, B)
- node T_159 = as-SInt(A)
+ node T_157 = addw(A, B)
+ node T_158 = subw(A, B)
+ node T_159 = asSInt(A)
node T_160 = dshr(T_159, shamt)
- node T_161 = as-UInt(T_160)
+ node T_161 = asUInt(T_160)
node T_162 = dshr(A, shamt)
node T_163 = dshl(A, shamt)
node T_164 = bits(T_163, 31, 0)
- node T_165 = convert(A)
- node T_166 = convert(B)
+ node T_165 = cvt(A)
+ node T_166 = cvt(B)
node T_167 = lt(T_165, T_166)
- node T_168 = as-UInt(T_167)
+ node T_168 = asUInt(T_167)
node T_169 = lt(A, B)
- node T_170 = as-UInt(T_169)
- node T_171 = bit-and(A, B)
- node T_172 = bit-or(A, B)
- node T_173 = bit-xor(A, B)
+ node T_170 = asUInt(T_169)
+ node T_171 = and(A, B)
+ node T_172 = or(A, B)
+ node T_173 = xor(A, B)
node T_174 = eq(UInt<4>(10), alu_op)
node T_175 = mux(T_174, A, B)
node T_176 = eq(UInt<4>(4), alu_op)
@@ -52,9 +52,9 @@ circuit ALUTop :
node T_195 = bits(oot, 31, 0)
out := T_195
node T_196 = bit(alu_op, 0)
- node T_197 = sub-wrap(UInt<1>(0), B)
+ node T_197 = subw(UInt<1>(0), B)
node T_198 = mux(T_196, T_197, B)
- node T_199 = add-wrap(A, T_198)
+ node T_199 = addw(A, T_198)
sum := T_199
module ALUdec :
input opcode : UInt<7>