Remove stanza (#231)

* Removed stanza implementation/tests.

In the future we can move the stanza tests over, but for now they should
be deleted.

* Added back integration .fir files

* Added Makefile to give Travis hooks

* Added firrtl script (was ignored before)

1 files changed, 0 insertions, 20 deletions

diff --git a/test/chirrtl/mask-bug.fir b/test/chirrtl/mask-bug.fir
deleted file mode 100644
index b580c075..00000000
--- a/test/chirrtl/mask-bug.fir
+++ /dev/null
@@ -1,20 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; CHECK: Done!
-circuit top :
-   module top :
-      input clk : Clock
-      wire p : UInt
-      wire q : UInt
-      cmem m : {a:UInt<4>,b:{c: UInt<4>,d:UInt<4>}}[10]
-      p <= UInt(1)
-      q <= UInt(1)
-      wire x : {a:UInt<4>,b:{c: UInt<4>,d:UInt<4>}}
-      x.a <= UInt(1)
-      x.b.c <= UInt(1)
-      x.b.d <= UInt(1)
-      when p :
-         write mport a = m[UInt(3)],clk
-         when q :
-            a <- x
-
-