diff options
| author | Jack Koenig | 2018-01-30 18:11:00 -0800 |
|---|---|---|
| committer | GitHub | 2018-01-30 18:11:00 -0800 |
| commit | 57025111d3bc872da726e31e3e9a1e4895593266 (patch) | |
| tree | 70de3e10760efef858ca78a4e181e28d30984abe /src/test | |
| parent | 47d2bb1f447644ee0bcc44701bc84018cc5795b9 (diff) | |
| parent | c9d3e257bff74235a75ff5530051e419b9ce8005 (diff) | |
Merge pull request #735 from freechipsproject/fix-const-prop
Fix Bugs in Constant Propagation
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/ConstantPropagationTests.scala | 25 |
1 files changed, 20 insertions, 5 deletions
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala index 06e24b97..e143f853 100644 --- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala +++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala @@ -67,9 +67,9 @@ s"""circuit Top : out <= in module Child : output out : UInt<1> - inst b of Bottom - b.in <= UInt(1) - out <= b.out + inst b0 of Bottom + b0.in <= UInt(1) + out <= b0.out module Top : input x : UInt<1> output z : UInt<1> @@ -91,8 +91,8 @@ s"""circuit Top : out <= UInt(1) module Child : output out : UInt<1> - inst b of Bottom - b.in <= UInt(1) + inst b0 of Bottom + b0.in <= UInt(1) out <= UInt(1) module Top : input x : UInt<1> @@ -712,6 +712,21 @@ class ConstantPropagationIntegrationSpec extends LowTransformSpec { execute(input, check, Seq(dontTouch("Top.z"))) } + "ConstProp" should "NOT optimize across dontTouch on registers" in { + val input = + """circuit Top : + | module Top : + | input clk : Clock + | input reset : UInt<1> + | output y : UInt<1> + | reg z : UInt<1>, clk + | y <= z + | z <= mux(reset, UInt<1>("h0"), z)""".stripMargin + val check = input + execute(input, check, Seq(dontTouch("Top.z"))) + } + + it should "NOT optimize across dontTouch on wires" in { val input = """circuit Top : |
