Merge pull request #1796 from ekiwi-sifive/scala-2.13-support

Scala 2.13 support

6 files changed, 16 insertions, 16 deletions

diff --git a/src/test/scala/firrtlTests/MultiThreadingSpec.scala b/src/test/scala/firrtlTests/MultiThreadingSpec.scala
index e41e6835..c7b18624 100644
--- a/src/test/scala/firrtlTests/MultiThreadingSpec.scala
+++ b/src/test/scala/firrtlTests/MultiThreadingSpec.scala
@@ -30,7 +30,7 @@ class MultiThreadingSpec extends FirrtlPropSpec {
 
     // Begin the actual test
 
-    val inputStrings = FileUtils.getLinesResource(inputFilePath)
+    val inputStrings = FileUtils.getLinesResource(inputFilePath).toSeq
 
     import ExecutionContext.Implicits.global
     try { // Use try-catch because error can manifest in many ways
diff --git a/src/test/scala/firrtlTests/ParserSpec.scala b/src/test/scala/firrtlTests/ParserSpec.scala
index ba5cb889..3d377901 100644
--- a/src/test/scala/firrtlTests/ParserSpec.scala
+++ b/src/test/scala/firrtlTests/ParserSpec.scala
@@ -21,7 +21,7 @@ class ParserSpec extends FirrtlFlatSpec {
                      "readwriter" -> "c"
                     )
     def fieldsToSeq(m: Map[String, String]): Seq[String] =
-      m map { case (k,v) => s"      ${k} => ${v}" } toSeq
+      m.map { case (k,v) => s"      ${k} => ${v}" }.toSeq
   }
 
   private object RegTests {
diff --git a/src/test/scala/firrtlTests/RemoveWiresSpec.scala b/src/test/scala/firrtlTests/RemoveWiresSpec.scala
index e6b60059..df3ceef6 100644
--- a/src/test/scala/firrtlTests/RemoveWiresSpec.scala
+++ b/src/test/scala/firrtlTests/RemoveWiresSpec.scala
@@ -37,7 +37,7 @@ class RemoveWiresSpec extends FirrtlFlatSpec {
     circuit.modules.head match {
       case Module(_,_,_, body) => onStmt(body)
     }
-    (nodes, wires)
+    (nodes.toSeq, wires.toSeq)
   }
 
   def orderedNames(circuit: Circuit): Seq[String] = {
@@ -55,7 +55,7 @@ class RemoveWiresSpec extends FirrtlFlatSpec {
     circuit.modules.head match {
       case Module(_,_,_, body) => onStmt(body)
     }
-    names
+    names.toSeq
   }
 
   "Remove Wires" should "turn wires and their single connect into nodes" in {
diff --git a/src/test/scala/firrtlTests/interval/IntervalMathSpec.scala b/src/test/scala/firrtlTests/interval/IntervalMathSpec.scala
index eeb70286..656e1f8c 100644
--- a/src/test/scala/firrtlTests/interval/IntervalMathSpec.scala
+++ b/src/test/scala/firrtlTests/interval/IntervalMathSpec.scala
@@ -19,24 +19,24 @@ class IntervalMathSpec extends FirrtlFlatSpec {
   val DShiftLeftPattern   = """.*output dshl.*<(\d+)>.*""".r
   val DShiftRightPattern  = """.*output dshr.*<(\d+)>.*""".r
   val ArithAssignPattern = """\s*(\w+) <= asSInt\(bits\((\w+)\((.*)\).*\)\)\s*""".r
-  def getBound(bound: String, value: Double): IsKnown = bound match {
-    case "[" => Closed(BigDecimal(value))
-    case "]" => Closed(BigDecimal(value))
-    case "(" => Open(BigDecimal(value))
-    case ")" => Open(BigDecimal(value))
+  def getBound(bound: String, value: BigDecimal): IsKnown = bound match {
+    case "[" => Closed(value)
+    case "]" => Closed(value)
+    case "(" => Open(value)
+    case ")" => Open(value)
   }
 
   val prec = 0.5
 
   for {
     lb1        <- Seq("[", "(")
-    lv1        <- Range.Double(-1.0, 1.0, prec)
-    uv1        <- if(lb1 == "[") Range.Double(lv1, 1.0, prec) else Range.Double(lv1 + prec, 1.0, prec)
+    lv1        <- Range.BigDecimal(-1.0, 1.0, prec)
+    uv1        <- if(lb1 == "[") Range.BigDecimal(lv1, 1.0, prec) else Range.BigDecimal(lv1 + prec, 1.0, prec)
     ub1        <- if (lv1 == uv1) Seq("]") else Seq("]", ")")
     bp1        <- 0 to 1
     lb2        <- Seq("[", "(")
-    lv2        <- Range.Double(-1.0, 1.0, prec)
-    uv2        <- if(lb2 == "[") Range.Double(lv2, 1.0, prec) else Range.Double(lv2 + prec, 1.0, prec)
+    lv2        <- Range.BigDecimal(-1.0, 1.0, prec)
+    uv2        <- if(lb2 == "[") Range.BigDecimal(lv2, 1.0, prec) else Range.BigDecimal(lv2 + prec, 1.0, prec)
     ub2        <- if (lv2 == uv2) Seq("]") else Seq("]", ")")
     bp2        <- 0 to 1
   } {
diff --git a/src/test/scala/firrtlTests/options/OptionParserSpec.scala b/src/test/scala/firrtlTests/options/OptionParserSpec.scala
index b8efbdb6..e93c9b2c 100644
--- a/src/test/scala/firrtlTests/options/OptionParserSpec.scala
+++ b/src/test/scala/firrtlTests/options/OptionParserSpec.scala
@@ -40,7 +40,7 @@ class OptionParserSpec extends AnyFlatSpec with Matchers with firrtl.testutils.U
     catchStatus { parser.terminate(Left("some message")) } should be (Left(1))
 
     info("exit status of 0 for success")
-    catchStatus { parser.terminate(Right(Unit)) } should be (Left(0))
+    catchStatus { parser.terminate(Right(())) } should be (Left(0))
   }
 
   it should "print to stderr on an invalid option" in new WithIntParser {
@@ -56,7 +56,7 @@ class OptionParserSpec extends AnyFlatSpec with Matchers with firrtl.testutils.U
     catchStatus { parser.terminate(Left("some message")) } should be (Right(()))
 
     info("no exit for success")
-    catchStatus { parser.terminate(Right(Unit)) } should be (Right(()))
+    catchStatus { parser.terminate(Right(())) } should be (Right(()))
   }
 
   behavior of "An OptionParser with DuplicateHandling mixed in"
diff --git a/src/test/scala/firrtlTests/options/PhaseManagerSpec.scala b/src/test/scala/firrtlTests/options/PhaseManagerSpec.scala
index d8422cb9..108f3730 100644
--- a/src/test/scala/firrtlTests/options/PhaseManagerSpec.scala
+++ b/src/test/scala/firrtlTests/options/PhaseManagerSpec.scala
@@ -392,7 +392,7 @@ class PhaseManagerSpec extends AnyFlatSpec with Matchers {
 
     /** Convert a Graphviz file to PNG using */
     def maybeToPng(f: File): Unit = try {
-      s"dot -Tpng -O ${f}" !
+      s"dot -Tpng -O ${f}".!
     } catch {
       case _: java.io.IOException =>
     }