diff options
| author | Albert Magyar | 2019-08-07 15:13:57 -0700 |
|---|---|---|
| committer | mergify[bot] | 2019-08-07 22:13:57 +0000 |
| commit | 23a104d3409385718a960427f1576f508e3f473b (patch) | |
| tree | 1bde53f80a0fe0f0c32eb0a1432f413989fd75b4 /src/test/scala | |
| parent | 0fe6aad23a4aee50119b9fe2645ba2ff833f65bb (diff) | |
DRY check chirrtl (#1148)
* Avoid redundancy between CheckChirrtl and CheckHighForm, add more checks
* Add test case for illegal Chirrtl memory in HighForm
Diffstat (limited to 'src/test/scala')
| -rw-r--r-- | src/test/scala/firrtlTests/CheckSpec.scala | 80 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/ChirrtlSpec.scala | 7 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/InternalErrorSpec.scala | 46 |
3 files changed, 28 insertions, 105 deletions
diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala index af16ec03..93bc2cab 100644 --- a/src/test/scala/firrtlTests/CheckSpec.scala +++ b/src/test/scala/firrtlTests/CheckSpec.scala @@ -2,18 +2,32 @@ package firrtlTests -import java.io._ import org.scalatest._ -import org.scalatest.prop._ import firrtl.{Parser, CircuitState, UnknownForm, Transform} import firrtl.ir.Circuit import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,PassException,InferWidths,CheckWidths,ResolveGenders,CheckGenders} class CheckSpec extends FlatSpec with Matchers { + val defaultPasses = Seq(ToWorkingIR, CheckHighForm) + def checkHighInput(input: String) = { + defaultPasses.foldLeft(Parser.parse(input.split("\n").toIterator)) { + (c: Circuit, p: Pass) => p.run(c) + } + } + + "CheckHighForm" should "disallow Chirrtl-style memories" in { + val input = + """circuit foo : + | module foo : + | input clock : Clock + | input addr : UInt<2> + | smem mem : UInt<1>[4]""".stripMargin + intercept[CheckHighForm.IllegalChirrtlMemException] { + checkHighInput(input) + } + } + "Memories with flip in the data type" should "throw an exception" in { - val passes = Seq( - ToWorkingIR, - CheckHighForm) val input = """circuit Unit : | module Unit : @@ -23,16 +37,11 @@ class CheckSpec extends FlatSpec with Matchers { | read-latency => 0 | write-latency => 1""".stripMargin intercept[CheckHighForm.MemWithFlipException] { - passes.foldLeft(Parser.parse(input.split("\n").toIterator)) { - (c: Circuit, p: Pass) => p.run(c) - } + checkHighInput(input) } } "Registers with flip in the type" should "throw an exception" in { - val passes = Seq( - ToWorkingIR, - CheckHighForm) val input = """circuit Unit : | module Unit : @@ -42,16 +51,11 @@ class CheckSpec extends FlatSpec with Matchers { | reg r : {a : UInt<32>, flip b : UInt<32>}, clk | out <= in""".stripMargin intercept[CheckHighForm.RegWithFlipException] { - passes.foldLeft(Parser.parse(input.split("\n").toIterator)) { - (c: Circuit, p: Pass) => p.run(c) - } + checkHighInput(input) } } "Instance loops a -> b -> a" should "be detected" in { - val passes = Seq( - ToWorkingIR, - CheckHighForm) val input = """ |circuit Foo : @@ -70,16 +74,11 @@ class CheckSpec extends FlatSpec with Matchers { | b <= foo.b """.stripMargin intercept[CheckHighForm.InstanceLoop] { - passes.foldLeft(Parser.parse(input.split("\n").toIterator)) { - (c: Circuit, p: Pass) => p.run(c) - } + checkHighInput(input) } } "Instance loops a -> b -> c -> a" should "be detected" in { - val passes = Seq( - ToWorkingIR, - CheckHighForm) val input = """ |circuit Dog : @@ -105,16 +104,11 @@ class CheckSpec extends FlatSpec with Matchers { | b <= foo.b | """.stripMargin intercept[CheckHighForm.InstanceLoop] { - passes.foldLeft(Parser.parse(input.split("\n").toIterator)) { - (c: Circuit, p: Pass) => p.run(c) - } + checkHighInput(input) } } "Instance loops a -> a" should "be detected" in { - val passes = Seq( - ToWorkingIR, - CheckHighForm) val input = """ |circuit Apple : @@ -126,16 +120,11 @@ class CheckSpec extends FlatSpec with Matchers { | b <= recurse_foo.b | """.stripMargin intercept[CheckHighForm.InstanceLoop] { - passes.foldLeft(Parser.parse(input.split("\n").toIterator)) { - (c: Circuit, p: Pass) => p.run(c) - } + checkHighInput(input) } } "Instance loops should not have false positives" should "be detected" in { - val passes = Seq( - ToWorkingIR, - CheckHighForm) val input = """ |circuit Hammer : @@ -158,10 +147,7 @@ class CheckSpec extends FlatSpec with Matchers { | output b : UInt<32> | b <= a | """.stripMargin - passes.foldLeft(Parser.parse(input.split("\n").toIterator)) { - (c: Circuit, p: Pass) => p.run(c) - } - + checkHighInput(input) } "Clock Types" should "be connectable" in { @@ -264,10 +250,6 @@ class CheckSpec extends FlatSpec with Matchers { for (op <- List("shl", "shr")) { s"$op by negative amount" should "result in an error" in { - val passes = Seq( - ToWorkingIR, - CheckHighForm - ) val amount = -1 val input = s"""circuit Unit : @@ -276,9 +258,7 @@ class CheckSpec extends FlatSpec with Matchers { | output z: UInt | z <= $op(x, $amount)""".stripMargin val exception = intercept[PassException] { - passes.foldLeft(Parser.parse(input.split("\n").toIterator)) { - (c: Circuit, p: Pass) => p.run(c) - } + checkHighInput(input) } exception.getMessage should include (s"Primop $op argument $amount < 0") } @@ -292,14 +272,8 @@ class CheckSpec extends FlatSpec with Matchers { | output foo : UInt | foo <= bits(in, 3, 4) | """.stripMargin - val passes = Seq( - ToWorkingIR, - CheckHighForm - ) val exception = intercept[PassException] { - passes.foldLeft(Parser.parse(input.split("\n").toIterator)) { - (c: Circuit, p: Pass) => p.run(c) - } + checkHighInput(input) } } diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala index 9344b861..aeb70c8d 100644 --- a/src/test/scala/firrtlTests/ChirrtlSpec.scala +++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala @@ -2,13 +2,8 @@ package firrtlTests -import java.io._ -import org.scalatest._ -import org.scalatest.prop._ -import firrtl.{Parser, CircuitState, UnknownForm, Transform} -import firrtl.ir.Circuit -import firrtl.passes._ import firrtl._ +import firrtl.passes._ class ChirrtlSpec extends FirrtlFlatSpec { def transforms = Seq( diff --git a/src/test/scala/firrtlTests/InternalErrorSpec.scala b/src/test/scala/firrtlTests/InternalErrorSpec.scala deleted file mode 100644 index 85c9c67d..00000000 --- a/src/test/scala/firrtlTests/InternalErrorSpec.scala +++ /dev/null @@ -1,46 +0,0 @@ -// See LICENSE for license details. - -package firrtlTests - -import java.io.File - -import firrtl._ -import firrtl.Utils.getThrowable -import firrtl.util.BackendCompilationUtilities -import org.scalatest.{FreeSpec, Matchers} - - -class InternalErrorSpec extends FreeSpec with Matchers with BackendCompilationUtilities { - "Unexpected exceptions" - { - val input = - """ - |circuit Dummy : - | module Dummy : - | input clock : Clock - | input x : UInt<1> - | output y : UInt<1> - | output io : { flip in : UInt<16>, out : UInt<16> } - | y <= shr(x, UInt(1)); this should generate an exception in PrimOps.scala:127. - | """.stripMargin - - var exception: Exception = null - "should throw a FIRRTLException" in { - val manager = new ExecutionOptionsManager("test") with HasFirrtlOptions { - commonOptions = CommonOptions(topName = "Dummy") - firrtlOptions = FirrtlExecutionOptions(firrtlSource = Some(input), compilerName = "low") - } - exception = intercept[FIRRTLException] { - firrtl.Driver.execute(manager) - } - } - - "should contain the expected string" in { - assert(exception.getMessage.contains("Internal Error! Please file an issue")) - } - - "should contain the name of the file originating the exception in the stack trace" in { - val first = true - assert(getThrowable(Some(exception), first).getStackTrace exists (_.getFileName.contains("PrimOps.scala"))) - } - } -} |
