Fix more problems with zero width things. (#779)

This should close #757. It should also allow for stop() and printf()
to be used with zero-width fields.

1 files changed, 36 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/ZeroWidthTests.scala b/src/test/scala/firrtlTests/ZeroWidthTests.scala
index 50385a80..6443e131 100644
--- a/src/test/scala/firrtlTests/ZeroWidthTests.scala
+++ b/src/test/scala/firrtlTests/ZeroWidthTests.scala
@@ -176,6 +176,42 @@ class ZeroWidthTests extends FirrtlFlatSpec {
         |    node a = cat(x, z)""".stripMargin
       (parse(exec(input)).serialize) should be (parse(check).serialize)
   }
+  "Stop with type <0>" should "be replaced with UInt(0)" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    input clk: Clock
+        |    input x: UInt<1>
+        |    input y: UInt<0>
+        |    input z: UInt<1>
+        |    stop(clk, y, 1)""".stripMargin
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    input clk: Clock
+        |    input x: UInt<1>
+        |    input z: UInt<1>
+        |    stop(clk, UInt(0), 1)""".stripMargin
+      (parse(exec(input)).serialize) should be (parse(check).serialize)
+  }
+  "Print with type <0>" should "be replaced with UInt(0)" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    input clk: Clock
+        |    input x: UInt<1>
+        |    input y: UInt<0>
+        |    input z: UInt<1>
+        |    printf(clk, UInt(1), "%d %d %d\n", x, y, z)""".stripMargin
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    input clk: Clock
+        |    input x: UInt<1>
+        |    input z: UInt<1>
+        |    printf(clk, UInt(1), "%d %d %d\n", x, UInt(0), z)""".stripMargin
+      (parse(exec(input)).serialize) should be (parse(check).serialize)
+  }
 }
 
 class ZeroWidthVerilog extends FirrtlFlatSpec {